Chapter 3l System design of a FORTRAN machine 379

9 to 5 transition. Fixed point constants are handled in state 6. The important difference is that the digits are not left adjusted in the SHR and a 04 is put into the program as the exponent since a decimal point is assumed to precede the first data word. See Fig. 1.

The ~ takes the circuit to its initial state. If this statement happens to be the last in a DO nest, the Statement Number Load circuit has set the LSFF to 1. It has also put the ST address of the word following the l symbol of the first DO of the nest into the SSAR register. Since the program counter (CP) now holds the correct exit address for this DO statement it is placed at the address given by the SSAR during the transition to state 0. During the transition the signal START READ is also sent to the paper tape reader in order for it to put the next Statement into the I/O buffer.

Each function mentioned in the paper plus some other auxiliary ones are initially represented in a state diagram form, such as the state diagram for the loading of the Arithmetic Statement (Fig. 5) and the Variable Match Unit (VMU) (Fig. 4).

We will describe the method used to realize a circuit which will perform the function defined by a given state diagram (SD). As an example we will use the VMU. All the information needed is present on the SD. The operations on the right-hand side of the "/,, in the SD are the output operations required to be performed. In order to implement these operations we must specify the actual register gating signals, memory read and write signals, arithmetic unit signals, etc., required by them. We will call these various signals the microsteps of an output operation. Therefore to realize the SD of a given function we must implement the microsteps corresponding to the output operations.

We begin by listing from the state diagram some output operations and their corresponding microsteps. For example, in state 2 of Fig. 4, if a MATCH signal is present we are supposed to increment the CIO counter and then read the I/O buffer.

Consequently the microsteps required are:

­ CIO This signal causes the CIO to be incremented by one.

CIO ® MAR This signal causes the CLO to be gated to the memory address register.

READ This signal initiates a memory read cycle.

CHANGE STATE This signal causes the VMU to go from state 2 to state 3.

Therefore the execution of the above microsteps, in that order, would implement the 2-3 transition of Fig. 4. Some microsteps for the VMU are listed at the end of this Appendix. The largest number of microsteps for a transition from one state to another is 8, which occurs in the transition from state 8 to state 2. Once this maximum number of microsteps is determined, a control cycle counter is constructed, which can count as high as this maximum. Since in this case the number is 8 we need 3 flip-flops to realize it. In addition, a "one hot line" decoder is needed such that at each count one and only one line of the decoder has a "one" at its output. Also needed is a state diagram counter which realizes the "skeleton" of the state diagram. This skeletal counter tells us which state we are in and which to change to, given the present input signal or symbol. Thus the skeletal counter "knows" that if the circuit is in state 2 and a MATCH signal is present, it should change to state 3 upon receipt of a change state signal. The realization of such a skeletal counter has been described [Bashkow, 1964]. Now we use the outputs of the skeletal counter which will indicate to us the state we are in, the outputs of the decoder of the control cycle counter, and the input lines ( S_v, S₀, MATCH, NO MATCH) and connect them as shown in Fig. 6. Each AND gate in this figure has 3 inputs except those not requiring input line information. One input comes from the input set (S₀, S_v, MATCH, etc.). The second input comes from the state diagram skeletal counter which indicates a unique state of the state diagram, and finally the third comes from the control cycle counter. The output of each AND gate is a line indicating a unique microstep. The AND's feed OR gates, which actually energize the given microstep. For example the output lead of the "READ" Or gate is connected to the "READ" terminal of the memory.

If we assume that the control cycle counts in sequence 1, 2, etc., then the lead numbered 1 will go to the first microstep of each sequence. The one numbered 2 will go the second, etc. Therefore we see that the following microsteps should be executed in the order listed below for states 0, 1, 2, 5 of Fig. 4. The circuit which causes the execution is shown in Fig. 6.

State 0 and START VMU

State 1 CIO ® SCIO

State 2 and MATCH