The ILLIAC IV computer1
George H. Barnes / Richard M. Brown / Maso Kato / David J. Kuck / Daniel L. Slotnick / Richard A. Stokes
Summary The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4 X 106 instructions per second to yield an effective rate of 109 operations per second.
Index terms Array, computer structure, look-ahead, machine language, parallel processing, speed, thin-film memory.
The study of a number of well-formulated but computationally massive problems is limited by the computing power of currently available or proposed computers. Some involve manipulations of very large matrices (e.g., linear programming); others, the solution of sets of partial differential equations over sizable grids (e.g., weather models); and others require extremely fast data correlation techniques (phased array signal processing). Substantive progress in these areas requires computing speeds several orders of magnitude greater than conventional computers.
At the same time, signal propagation speeds represent a serious barrier to increasing the speed of strictly sequential computers. Thus, in recent years a variety of techniques have been introduced to overlap the functions required in sequential processing, e.g., multiphased memories, program look-ahead, and pipeline arithmetic units. Incremental speed gains have been achieved but at considerable cost in hardware and complexity with accompanying problems in machine checkout and reliability.
The use of explicit parallelism of operation rather than overlapping of subfunctions offers the possibility of speeds which increase linearly with the number of gates, and consequently has been explored in several designs [Slotnick et al., 1962; Unger, 1958; Holland, 1959; Murtha, 1966]. The SOLOMON computer [Slotnick et al., 1962], which introduced a large degree of overt parallelism into its structure, had four principal features.
1 A large array of arithmetic units was controlled by a single control unit so that a single instruction stream sequenced the processing of many data streams.
2 Memory addresses and data common to all of the data processing were broadcast from the central control.
3 Some amount of local control at the individual processing element level was obtained by permitting each element to enable or disable the execution of the common instructions according to local tests.
4 Processing elements in the array had nearest-neighbor connections to provide moderate coupling for data exchange.
Studies with the original SOLOMON computer indicated that such a parallel approach was both feasible and applicable to a variety of important computational areas. The advent of LSI circuitry, or at least medium-scale versions, with gate times of the order of 2 to 5 ns, suggested that a SOLOMON-type array of potentially 109 word operations per second could be realized. In addition, memory technology had advanced sufficiently to indicate that 106 words of memory with 200 to 500-ns cycle times could be produced at acceptable cost. The ILLIAC IV Phase I design study during the latter part of 1966 resulted in the design discussed in this paper. The machine, to be fabricated by the Defense Space and Special Systems Division of Burroughs Corporation, Paoli, Pa., is scheduled for installation in early 1970.
Summary of the ILLIAC IV
The ILLIAC IV main structure consists of 256 processing elements arranged in four reconfigurable SOLOMON-type arrays of 64 processors each. The individual processors have a 240-ns ADD time and a 400-as MULTIPLY time for 64-bit operands. Each processor requires approximately 104 ECL gates and is provided with 2048 words of 240-ns cycle time thin-film memory.
Instruction and addressing control
The ILLIAC LV array possesses a common control unit which decodes the instructions and generates control signals for all
1IEEE Trans., C-17~ vol. 8, pp. 746-757, August, 1968.