Chapter 2l Design of an arithmetic unit incorporating a nesting store 263
add (forming c + de)
divide (forming f),
store as f(leaving the nesting store in the same state as before the fetch a instruction).
For instructions, the 48-hit word has been divided into 6 syllables of eight bits each, and these are then treated as a continuous sequence of variable length instructions. Arithmetic operations are specified by single syllable instructions, but main store transfers require three syllables to accommodate both the address and the address modifying information of the word to which they refer; jump instructions also have three syllables. Two-syllable instructions include the peripheral transfers, and instructions for processing address modifiers and performing shifts. The first syllable of every instruction contains two bits whose values specify the length of the instruction; the redundant case being used to differentiate between main store transfers and jump instructions. The first syllable of an instruction contains enough information to specify any arithmetic unit operation required; thus in the machine, each instruction is treated by two controls; the first or Store Control organising the fetching and storing of information in advance of the second or Arithmetic Unit Control which completes the instruction on the information in the first syllable.
Range of functions
The allocation of bits to the instructions described above allows 64 possible functions, of which 59 are used to specify the wide range of operations needed in a general purpose computer.
As well as the normal single-length fixed-point arithmetic operations, functions have been provided for the addition and subtraction of double-length numbers. These simplify the programming of multi-length operations as well as giving increased accuracy. For normal scientific and engineering calculations automatic floating-point facilities are available. A single length word may represent a floating-point number with a 40-bit fractional part f, and an 8-bit characteristic c; the value of the number is then f2c-128. The fractional part is limited to the range -1 < f < -1/2, or 1> f > 1/2, or f = 0 when c is also zero. All floating-point operations assume that operands are in this standard form and give correctly rounded results in standard form. Functions for the addition and subtraction of double-length floating-point numbers have been provided, as these give increased accuracy and stability in many matrix operations.
An increase in operating speed and a saving of instructions are effected by the use of instructions which re-order the position of information in the most accessible cells of the nesting store, including reversing and cycling operations. The normal logical operations are provided.
All arithmetic operations in the arithmetic unit are carried out on binary numbers using the two's-complement notation for negative numbers; instructions being provided for the conversion to and from binary of information stored as 6-bit characters in other radix systems. For the convenience of the programmer, double-length numbers are stored in the arithmetic unit with their more significant half in a more accessible cell; the sign of the less significant half is ignored and is set positive after all double-length operations.
The nesting store
Although the concept of a nesting store is similar to that of a rifle magazine where the addition of a cartridge displaces those already there, movement of information only occurs in the three most accessible cells of the nesting store, which are transistor flip-flop registers forming part of the arithmetic unit. The less accessible cells are core registers which are addressed in a sequential manner by a reversible counter. Reading from these cores reduces the count by one, thus selecting the next word; the read-out is destructive so that the cores are in the correct state for a subsequent writing operation, which is the reverse of a read. The access time of the cores is reduced by providing separate counters and reading and writing mechanisms for the odd and even numbered rows of cores; thus when reading or writing from odd rows the addressing mechanism for the next even row is set, so that it is available for immediate use. Thus with a simple one core per bit system successive reads can be made at 1 m sec intervals and writes at 2 m sec intervals; as these operations are performed in parallel with the functioning of the arithmetic unit, their times do not increase the time required to complete the functions.
The arithmetic unit
As shown in Fig. 1, there are six full length transistor flip-flop registers in the arithmetic unit; there are also two 8-bit registers used when performing floating-point operations. The main facilities associated with these registers are as follows.
W1, W2 and W3 are the three most accessible cells of the nesting store; transfers to the core part of the nesting store, being