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Chapter 18 The IBM 1401 227

Function of instruction characters:

C[0] op code; always contains a word-mark flag or F bit.
C[l, 2, 3] = branch address for I_ Address register or first operand address for the A_ Address register.
C[1] or C[4] or C[7] d_ character; used as a single character for additional operation code information or a character for comparison, or to select a test.
C[4, 5, 6] primary operand (B_ Address register specification).

character strings, {char.string}, and the state diagram accounts for strings on a character-at-a-time basis. For an add instruction Fig. 3 oversimplifies the execution because it implies that each character of the A and B operand is accessed, the addition is performed, and the result is restored according to the B_ address register. A more complex description must account for A and B strings of unequal length, and the case of getting a number which must be recomplemented because it is the wrong sign. The recomplementation process requires a reverse scan to find the end of the B string and then a forward scan to recomplement each character of B. Figure 4 is a detailed state diagram of the add execution process.

The states in the ISP description (Appendix 1) within the instruction-interpretation process correspond to the three state types just described: the single-instruction character-fetch operation, the fetch-operand-addresses for the remainder of the instruction, and Instruction_ execution. Instruction_ execution is not given in any detail. For example, the execution of add is defined as "A"(: = op = 110001) ® Ovÿ M[B] ¬ M[B] + M[A] {char.string};. The state diagram (Fig. 4) presents this execution in detail. Note that in the ISP description we omit telling the reader that the A and B address registers point to the next lowest variable-length string in M after an operation is performed. We allow the definition of a variable-string operation, for example, + {char.string}, to imply the action on the processor state.

Some instructions can be defined with a single character, and these are called chained instructions. Chained instructions take the previous values of the pointer registers, the A and B address registers, as the operand addresses. The add instruction, for example, can be either 1 (chained), 4, or 7 characters; the forms of all instructions appear in Table 1. The 4-character add instruction places the A address field in both the A and B address registers; thus the effect is an instruction to double a string (add it to itself).


An n-decimal-digit numeric data string is represented as

C[n - 1], C[n - 2], . . . , C[1], C[0], C[M]

The underlined characters, C[n - 1] and C[M], have the flag bit present, that is, (C[n - 1]á Fñ = 1) and (C[M]á Fñ = 1). The n characters are stored in locations Mp[j], Mp[j + 1],... , Mp[j +

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