previous | contents | next

226 Part 3 The instruction-set processor level: variations in the processor

Section 3 Processors for variable-length-string data

instructions are necessary for subroutines-the Store Address Register Feature; Indexing Feature; Multiply-Divide Feature; High-Low-Equal Compare Feature; Read Release and Punch Release Feature; the Column Binary Feature; Early-Card-Read Feature; Processing Overlap Feature, etc.

PMS structure

The 1401 PMS structure (Fig. 2) is an early 1 Pc structure. The diagram does not show the S(fixed) Pc interconnection structure with the Ms and T. The Pc-(Ms ÷ T) interconnection restricts the concurrency of T and Ms. The optional processing overlap feature provides a link to Mp to allow the T(card; read, punch) to be run concurrently with Pc processing. When any of the peripheral devices are operating without the processing overlap feature, the Pc is dedicated to be a data transmission link or K (as in earlier computers). The device K is connected directly to Pc. For example, Ms(disk, magnetic tape) data transfers use the main registers of the Pc and can tie it up full time during data transmission. By careful programming, several devices can be synchronized and thus run concurrently for communicating with Pc from a K. The Pc does not have an interrupt system. Thus the peripherals have no way of communicating with Pc. Subsequent models, the 1440 and 1460, added interrupt capability and made it easier to control multiple simultaneous data transfers among the peripheral K's and Pc.

Fig. 2. IBM 1401 PMS diagram.

ISP structure

The IBM 1401 ISP is given in Appendix 1 of this chapter. Instruction strings and data strings are delimited by the special F bit in a character. A character in Mp is of the form'

Cá check,F,B',A', 8, 4, 2, 1ñ

An n-character string is C[0], C[1], --- C[n - 1]

and would be stored in Mp[j:j + n - 1]

The first character (or head) of an instruction must contain the word-mark flag or F bit. The head of the instruction, which is to be interpreted next, is held at Mp[I], and' succeeding characters of the instruction are at Mp[I + 1], Mp[I + 2], etc. Correctly defined instructions are 1, 2, 4, 5, 7, and 8 characters long. Undefined instruction lengths of up to 8 characters are also interpreted without an error condition. The interpretation algorithm presented in the ISP description does not explain the action of instructions which have an incorrect length. Actually, the 1401 Reference Manual does not go into details of general instruction interpretation but dwells on "correct" operation. Table 1 presents the correct instruction lengths and formats. If we take the instructions in the table, the set is not variable in length but is fixed at these six sizes. The instruction set (not including the input/output instructions) is presented in Table 2. This table also provides a hint of the implementation, since the execution times are given in terms of memory cycles.

The ISP state, unlike that of more conventional processors, has no temporary operand storage (e.g., accumulators). The ISP state has registers which point to operands. The state of the machine (see Appendix 1) is basically: Mp, the Instruction Location Counter, Indicators or miscellaneous bits, three 3-character blocks of Mp reserved for Index registers, and the two registers A_ address and B_ address which point to data operands.

Instruction interpretation

There are three principal state types in processing an instruction: o.q., when the instruction is being formed; o.v., when the operands are being accessed or the results are being stored in Mp; and o, when the operation specified by the instruction is being carried out. Each state transition corresponds essentially to a memory access. The three instruction types of Fig. 3 each have their own particular states. Only types 1 and 2 process the variable-length

1See Appendix 1 of this chapter for the meaning of the hits in a character. We have renamed the A and B bits A' and B' to avoid confusion with the registers.

previous | contents | next