previous | contents | next

204 Part 3 ô The instruction-set processor level: variations in the processor

Section 1 Processors with greater than 1 address per instruction

The instruction ARW has thus been repeated p times when the drum address of the repeating instruction is 8l92-2p. This way of repeating an instruction has made it possible to do multiplication, division, block transfers, table look up and many other small basic repetitive processes in a very simple way. There is no special hardware present in the machine to do the counting necessary for the repetition, as this counting is done by the normal address counter.

As a last example we shall give a programme for the summation of a block of locations from 200 to 300 in the store. This involves 101 locations. The programme reads:

100 A10IBC Put A200Q in B (B has address 3).

101 A200Q

102 X103KE4C Put return jump X104 in 4. Clear A in advance.

103 X7990K3W Repeat A200Q 101 times. Because A200Q is standing in B the 9 augments the instruction itself at every repetition. Hence

104 etc. successively á 200ñ á 201ñ etc. are added to A. At the end the sum is left in A and

the programme proceeds at 104.

It is left to the reader to work out the action diagram.

This example is not programmed for minimum waiting, but by supplying the repeating instruction X7990K3W with a Q it will step up the repeated instruction A200Q by 2 every time. Now, once the first instruction has been located, all even locations following are emerging from the drum just at the right time. The odd numbered locations must be summed in a second, similar repetition.


VandW59; VandW52, 56; WilkM53a.

previous | contents | next