90 Part 2 The instruction-set processor: main-line computers
Section 1 Processors with one address per instruction
emulate it, making incremental modifications to it, and completely redesigning it.1
The PDP-8, although not the first 12-bit computer, achieved a status that made it the first standard for small, low cost dedicated computers. There is an active market now for computers in this size and price range to which the marketing culture has responded with the names microcomputer, minicomputer and midicomputer for 8- to 12-, 12- to 16- and 16- to 24-bit word-length computers, respectively.2
The PDP-8 has a nearly minimal processor state because the address and ISP integers are 12 bits. Twelve bits is just large enough to represent data from external physical process environments (analog signals) and also just right to address a 4096 word memory. System software (editors, assemblers, compilers, etc.) can surprisingly all fit into this sized memory.3 The processor state is only 26 bits, and the predecessor PDP-5 had a hardwired state of only 14 bits.
The PDP-8 is also discussed in Part 5, Sec. 2, page 396.
The Whirlwind I computer
Whirlwind I is based on Wilkes' EDSAC at Manchester University. Chapter 6 describes the computer and gives a brief description of vacuum-tube logic and electrostatic storage-tube technology. The PMS structure of Whirlwind I with core memory is given in Fig. 1.
The Memory Test Computer (MTC) of M.I.T.'s Lincoln Laboratory was the first computer to use a core memory. MTC was built to test the memory which Whirlwind I received in August, 1953. Subsequent modifications included the addition of another 2,048-word magnetic-core memory in September, 1953.
The machine's construction and technology are outstanding. It has effective marginal checking and preventive-maintenance test facilities. At the time the machine was dismembered and moved from MIT., it had a use time availability of greater than 95 percent. Although Whirlwind I left M.I.T. in 1960, the machine was reassembled and was operational as late as 1966.
The machine's PMS structure is a simple 1 Pc. The K to Mp block transfers are via the Pc on a one-at-a-time, programmed basis. A single data transfer can be initiated to a particular device, thus providing some opportunity for input/output and processing concurrency. The simple structure is due to the high
Fig. 1. Whirlwind I PMS diagram.
register costs of the vacuum-tube technology; thus only a single central processor register is provided to hold (or buffer) data during a K transmission to a T or Ms. Appendix 1 of Chap. 6, which is from the programming manual, gives its instruction set.
The IBM 1800
The IBM 1800 (Chap. 33) is a third-generation, 16-bit computer. It is discussed in Part 5, Sec. 2, page 396.
Some aspects of the logical design of a control computer: a case study
Chapter 7 presents the aerospace computer Apollo designed by MIT's Instrumentation Laboratory. It is presented in contrast to the general-purpose 16-bit computers, Whirlwind (Chap. 6) and the IBM 1800 (Chap. 33). The Apollo computer uses a M(read only) because it is obviously a problem to reload programs. Kampe's SD-2 (Chap. 29) and Apollo (Chap. 7) are both controllers and have other similar design constraints. The IBM 1800 is also used for control purposes. In fact, the computers in this section up to and including the 24-bit SDS 910-9300 series are all designed for control environments. However, all the latter machines have a goal of generality not present in the Apollo.
1Perhaps also because of one of the author's (GB) obvious attachment.
2See the computers in this size range chapter 3, Figure 2, page 43.
3Conceivably a corollary to Parkinson's law: Programs expand to fill every word in the primary memory of a computer.