302 THE PDP-11 FAMILY
Figure 1. On one 21.6 cm X 26.7 cm board, the LSI -11 provides a complete PDP-11 processor, 4 Kwords of 16-bit memory, an ASCII console, a real-time clock, an automatic dynamic memory refresh, and interface bus control.
one; the choice was made on the basis of total system cost and performance. On this basis, a microprogrammed processor was selected, permitting the inclusion of features like a "zero cost" real-time clock and automatic dynamic memory refresh. The built-in ASCII programmer's console was also made feasible by the LSI-l l's microprogrammed nature.
Awareness of system costs and performance, then, was a primary motivation in the LSI-l1 design. System issues include cost and ease of interconnection, the customer's investment in training and software, and the availability of design support for both hardware and software. The impact of these system concerns should become apparent in the following sections which detail the LSI-11 design. Two viewpoints are taken in this description: the first section treats the internals of the LSI-11 from the computer designer's point of view, while the second considers the system from the user's perspective. The former examines the architecture, organization, and implementation of the LSI-11, while the latter discusses interfacing, special features, and PDP-11 compatibility. Together, these two viewpoints will provide the reader with an introduction to the DEC LSI-11, the first micro programmed minicomputer-compatible LSI microcomputer, which provides minicomputer performance at a microcomputer price.
THE COMPUTER DESIGNER'S VIEW
For the purpose of this discussion, the design of the LSI-l 1 will be studied at the following three levels: (1) architecture - the machine as seen by the programmer, (2) organization - the block diagram view of subsystems and their interconnection, and (3) implementation - the actual fabrication and physical arrangement of the various pieces at the component level.
Instruction Set. The architectural level of a computer system includes its instruction set, address space, and interrupt structure. The basic LSI-l1 instruction set is that of the PDP-11/40, without memory mapping. These instructions include several operations not found in other small PDP-l1 processors, such as Exclusive-Or (XOR), Sign-Extend (SXT), Subtract One and Branch (SOB), etc. Full integer multiply/divide (Extended Instruction Set or EIS) and floating- point arithmetic (Floating Instruction Set or FIS) may be provided by the addition of a single control read-only memory chip (to be discussed later). Unlike other PDP-11s, there are two special operation codes which facilitate access to the processor's program status word (PSW). The instruction set is, then, more comprehensive than that of the PDP-11/05, while the execution times (see Table 1) are a little slower.
To take advantage of the microprogrammed nature of the LSI-1 1, it may at times be desirable to invoke a user-written microroutine. This