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Photos courtesy of
The Computer Museum History Center |
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Please only copy with credit! |
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http://www.computerhistory.org |
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Largest computer at a given time |
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Technical use for science and engineering
calculations |
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Large government defense, weather, aero
laboratories are first buyers |
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Price is no object |
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Market size is 3-5 |
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10T • |
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1T • |
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100G • |
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10G • |
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1G • |
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100M • |
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10M • |
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1M • |
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100K • |
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10K • |
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1K • |
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100 • |
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10 • |
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When scientific processing was 100% of the
industry a good predictor |
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$3 Billion: 6 vendors, 7 architectures |
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DOE buys 3 very big ($100-$200 M) machines every
3-4 years |
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Time $M structure example |
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1950 1 mainframes many... |
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1960 3 instruction //sm IBM / CDC |
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mainframe SMP |
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1970 10 pipelining 7600 / Cray 1 |
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1980 30 vectors; SCI “Crays” |
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1990 250 MIMDs: mC, SMP,
DSM “Crays”/MPP |
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2000 1,000 ASCI, COTS MPP Grid, Legion |
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Intra processor |
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Memory overlap & instruction lookahead |
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Functional parallelism (2-4) |
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Pipelining (10) |
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SIMD ala ILLIAC 2d array of 64 pe vs vectors |
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Wide instruction word (2-4) |
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MTA (10-20) |
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MIMDs… processor replication |
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SMP (4-64) |
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Distributed Shared Memory SMPs 100 |
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MIMD… computer replication |
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Multicomputers aka MPP aka clusters (10K) |
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Grid: 100K |
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1950 . 1960 . 1970 . 1980 . 1990 . 2000 |
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Vtubes Trans. MSI(mini) Micro
RISC nMicr |
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Processor overlap, lookahead “killer
micros” |
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Cray era 6600 7600 Cray1 X
Y C T |
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Vector-----SMP----------------> |
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SMP mainframes---> “multis”-----------> |
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DSM KSR SGI----> |
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Clusters Tandm VAX IBM UNIX-> |
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MPP if n>1000 Ncube
Intel IBM-> |
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Networks
n>10,000 NOW Grid |
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1950 . 1960 . 1970 . 1980 . 1990 . 2000 |
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Vtubes Trans. MSI(mini) Micro
RISC nMicr |
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Sequential programming---->------------------------------ |
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<SIMD
Vector--//--------------- |
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Parallelization--- |
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Parallel programming <--------------- |
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multicomputers <--MPP era------ |
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ultracomputers 10X in price 10xMPP |
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“in situ” resources 100x in //sm NOW VLC |
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Grid |
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Packaging, including heat removal |
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High level bit plumbing… getting the bits from
I/O, into memory through a processor and back to memory and to I/O |
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Parallelism |
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Programming: O/S and compiler |
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Problems being solved |
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1951: ERA 1103 control circuits |
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1957: Sperry Rand NTDS; to CDC |
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1959: Little Character to test transistor ckts |
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1960: CDC 1604 (3600, 3800) & 160/160A |
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1964: CDC 6600 (6xxx series) |
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1969: CDC 7600 |
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1976: Cray 1...
(1/M, 1/S, XMP, YMP, C90, T90) |
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1985: Cray Computer
Cray 2 from Cray Research;
GaAs: Cray 3 (1993), Cray 4 |
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1999: SRC Company large scale,
shared memory multiprocessor using x86 microprocessors |
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Creative and productive during his entire career
1951-1996. |
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Creator and un-disputed designer of supers from
c1960 1604 to Cray 1, 1s, 1m c1977… basis for
SMPvector: XMP, YMP, T90, C90, 2, 3 |
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Circuits, packaging, and cooling… |
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“the mini” as a peripheral computer |
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Use I/O computers versus I/O processors |
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Use the main processor and interrupt it for I/O
versus I/O processors aka IBM Channels |
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Multi-theaded processor (6600 PPUs) |
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CDC 6600 functional parallelism leading to RISC…
software control |
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Pipelining in the 7600 leading to... |
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Use of vector registers: adopted by 10+
companies.
Mainstream for technical computing |
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Established the template for vector
supercomputer architecture |
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SRC Company use of x86 micro in 1986 that could
lead to largest, smP? |
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SIMDs |
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Illiac IV |
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CDC Star |
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Cray 1 |
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Minisupers with VLIW attack the market |
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Like the minisupers, they are repelled |
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It’s software, software, and software |
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Was it a basically good idea that will now work
as Merced? |
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A less costly, CM 1/2 done in silicon chips |
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It is repelled. |
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S is the fatal flaw |
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Danny Hillis
1990 (1 paper or 1
company) |
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My goal was not necessarily to just win the bet! |
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Hennessey and Patterson were to evaluate what
was really happening… |
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Wanted to understand degree of MPP progress and
programmability |
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ATT/Columbia (Non Von), BBN Labs,
Bell Labs/Columbia (DADO),
CMU Warp (GE & Honeywell),
CMU (Production Systems), Encore, ESL, GE (like connection machine),
Georgia Tech, Hughes (dataflow), IBM (RP3), MIT/Harris, MIT/Motorola
(Dataflow), MIT Lincoln Labs, Princeton (MMMP), Schlumberger (FAIM-1),
SDC/Burroughs, SRI (Eazyflow),
University of Texas,
Thinking Machines (Connection Machine), |
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Alliant, American Supercomputer, Ametek,
AMT, Astronautics, BBN Supercomputer, Biin, CDC, Chen Systems, CHOPP,
Cogent, Convex (now HP), Culler, Cray Computers, Cydrome, Dennelcor,
Elexsi, ETA, E & S Supercomputers, Flexible, Floating Point Systems, Gould/SEL,
IPM, Key, KSR, MasPar, Multiflow, Myrias, Ncube, Pixar, Prisma, SAXPY, SCS,
SDSA, Supertek (now Cray), Suprenum, Stardent (Ardent+Stellar),
Supercomputer Systems Inc., Synapse, Thinking Machines, Vitec, Vitesse,
Wavetracer. |
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Intel/Sandia:
9000x1 node Ppro |
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LLNL/IBM:
512x8 PowerPC (SP2) |
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LANL/Cray:
6144 CPUs |
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Maui Supercomputer Center |
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512x1 SP2 |
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12,000 sq. ft. of floor space |
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1.6 MWatts of power |
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530 tons of cooling |
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384 cabinets to house 6144 CPU’s with 1536 GB
(32GB / 128 CPUs) |
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48 cabinets for metarouters |
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96 cabinets for 76 TB of raid disks |
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36 x HIPPI-800 switch Cluster Interconnect |
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9 cabinets for 36 HIPPI switches |
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about
348 miles of fiber cable |
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Computing nodes
speed: 9.6 Gflops vector, 1.2 Gflops scalar
primary memory: 4-16 GB
memory bandwidth: 76 GB/s (9.6 x 64 Gb/s)
inter-processor comm: 1.6 GB/s non-blocking
with global addressing among all nodes
I/O: 3 GB/s to scsi, hippi, gigabit ethernet, etc. |
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1-128 computers deliver 1.22 Tflops |
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SMPv computing nodes |
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4 - 8 processors/computer |
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Processor pap: 8 Gflops |
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Memory |
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I/O speed |
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Cluster |
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Raceway and (RACE++) Busses |
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ANSI Standardized |
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Mapped Memory, Message Passing, ‘Planned Direct’
Transfers |
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Circuit Switched; Basic Bus Interface Unit Is a 6 (8) Port Bidirectional Switch
at 40MB/s (66MB/s) Per Port. |
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Scales to » 4000 Processors |
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Skychannel |
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ANSI Standardized |
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320mb/sec; Crossbar backplane supports up to 1.6
GB/s Throughput Non-blocking |
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Heart of Air Force $3M / 256 Gflops System |
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Rugged System With 10 Modules ~ $100K; $1K /# |
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Scalable to several K processors; ~1-10 Gflop /
Ft3 |
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10 9U Boards * 4 Ppc750’s » 440 Specfp95 in
1 Ft3 (18.5 * 8 * 10.75”) |
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Sky 384 Signal Processor, #20 on ‘Top 500’, $3M |
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Mechanical: cooling and signals |
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Chips: design tools, fabrication |
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Chips: memory, PIM |
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Architecture: mta on steroids |
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Storage material |
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Mead 11 year rule: time between lab appearance
and commercial use |
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Requires >2 break throughs |
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Team’s first computer or super |
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It’s government funded…
albeit at a university |
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Notes