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Section 1

Processors with greater than 1 address per instruction

Multiple-address instruction formats exist for several reasons. The addition of an explicit address to determine the next instruction occurs with cyclic Mp's to make them efficient. Section 2 is devoted to this case, and it will not be considered further here. These processors are known as n + 1 address. A second reason is that many operations have more than one operand (as in A + B or A V B), and it seems to be efficient encoding to put them all into an instruction. A third reason is that many operations need to be followed by writing the result in memory, to permit the Pc to be used for operations on other data. Thus, coupling each operation with the address where the result is to be stored seems to be advantageous. However, in evaluating complex arithmetic expressions, more instruction bits and memory references are required than in a single-address computer. Also, for unary operators one address field is unused. It seems fair to say that ISP organizations with two or three addresses have not proved themselves in competition with the main line of 1(1 + index), or(1 + general register) organizations. However, no definitive demonstration of their inefficiency under all technological conditions exists, and they are worth studying.

For microprogrammed processors, multiple-address instructions allow a high degree of parallelism to be obtained in a single instruction. Multiple-address formats survive in this form.

The Pilot ACE

The National Physics Laboratory's Pilot ACE is the first of several cyclic memory computers which have been designed to provide optimum coding of instructions. Subsequent machines which it influenced include the nearly identical English Electric Deuce, the Bendix G-15, and the Packard Bell PB-250.1 The PMS structure does not strictly follow our lattice model (page 65). The Deuce PMS structure is given in Fig. 1. A 32-word block in Mp.delay_ line can be transferred to Ms.drum in one instruction (transfer time of 1,024 m s). Another capability of ACE allows it to perform operations on vectors of up to 32 elements in 1 instruction.

The ACE structure (Chap. 11) has a common M which contains much of the processor state and Mp. Many of the locations used for processor state can store programs for direct execution. The diagram on page 198 in Chap. 11 describes the instruction execution process and implementation.

Alan M. Turing is credited with the basic design of ACE (see introduction, page 193, and Turing's biography [Turing, 1959]).

ZEBRA, a simple binary computer

ZEBRA illustrates the organizational details of another serial arithmetic computer with Mp.cyclic. ZEBRA, like ACE, allows the user to construct instructions for the hardware which are almost directly interpreted. In both ACE and ZEBRA very little decoding is built into the machine; a large instruction set is available since the instructions are microcoded. In these computers the programming problem can be as complex as the user wishes, because a large number of different instructions can be micro-

Fig. 1. English Electric Deuce PMS diagram.

1H. D. Huskey was involved in the design of ACE, G-15, and PB-250; he was undoubtedly the idea carrier.


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