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Part 3

The instruction-set processor level: variations in the processor

In this part we discuss computers whose ISP's are variations from the main-line computers in Part 2. These variations represent historical computers that have not remained viable in the judgment of the computer engineering community, responses to particular technology, and explorations that were either too advanced for their time or still exist as open options.

Section 1, Processors with greater than 1 address per instruction, is mostly of historical and comparative interest. The general register organization with large Mp's (hence large addresses) almost surely dominate them.

Section 2, Processors constrained by a cyclic, primary memory, describes a response to a historical feature of Mp technology. The use of a drum, delay line, or disk was a matter of necessity rather than choice. When better random access core memories were available, the drum ceased to be a primary memory component.

Section 3 presents processors for variable string data. These processors are no longer built in their original form. However, they were very successful for a while (IBM 1401). Furthermore, string data-types have been incorporated in later processors.

Section 4 presents two desk calculator computers. Although we too often dismiss these devices as mere desk calculators, they have facilities that qualify them as general purpose stored program computers. Unlike most computers, because of the production cost constraint, these calculator computers are all very cleverly designed.

Section 5, Processors with stack memories, describes an organization that has never reached the main line state. Nevertheless, the idea of a stack memory is gradually being assimilated. For example, the DEC PDP-6 and PDP-10 computers use their general registers for stack pointer control, as suggested in Chap. 3, page 62.

In Sec. 6 the ideas of multiprogramming are presented. These ideas are recent and have not yet been adequately incorporated in main line designs. They undoubtedly will be standard features in the next generation, although the exact form cannot yet be known.


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