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Section 2

Processors with a general register state

The processors described in this section all have a processor state consisting of registers which are used for multiple (i.e., general) purposes. Perhaps a better name might be processors with a state consisting of a register array(s). The following machines are fairly similar in their ISP structure: Pegasus (Chap. 9), the DEC PDP-6,10, the SDS Sigma 5 and 7, and the UNIVAC 1107 and 1108. However, other computers including an 8-bit character computer (Chap. 10) and the CDC 6600 (Chap. 39) also use arrays of registers.

The general register organization appears as a compromise between the 1 and 2 address organizations. It avoids some of the extra instructions for shuffling data, inherent in a 1 address system, but avoids taking the space for a full additional address. The index register organization is also such a compromise, but one that is specialized to address calculations. The general register organization moves further toward a full 2 address organization without much additional cost. This assumes a small relative cost for a small amount of memory that is significantly faster than the larger Mp.

The design philosophy of Pegasus, a quantity-production computer

Chapter 9 describes Pegasus's logical organization and the technology from which it was implemented. The technology includes vacuum tubes, a cyclic memory, and dynamic logic based on delay lines. Pegasus has the nicest ISP processor structure discussed in this section-perhaps in the book. It is included because it is probably the first machine to use an array of general registers as accumulators, multiplier-quotient registers, index registers, etc. This ISP organization should be compared with the IBM System/360 (Chap. 43). Note that the multiple-register organization is independent of Mp.cyclic. This organization improves performance by generality.

The structure of System/360 Part I-outline of the logical structure

The IBM System/360 is described in Part 6, Sec. 3, and is included mainly because of the very large number of such systems that have been built.

An 8-bit-character computer

This computer (Chap. 10) has been invented by the authors to show the composite features of a small character/word-oriented computer. In reality, 8-bit machines turn out to look either like 16-bit machines, because the Mp size accessed is usually >28 words, or like character-string processors. Because of the primitive nature of this machine, it is a possible alternative to the larger more complex microprogrammed processors for defining more complex ISP's.

Parallel operation in the Control Data 6600

The CDC 6600, described in Chap. 39, has three arrays of eight registers each. Two of the arrays are used rather generally, and the third array is used to access words in Mp. The design of the CDC 6600 is a classic because of the computing power it provides. It is also worth studying as an example of a Pc assigned exclusively to data operation, with all concern with the larger PMS structure located in Pio's. A discussion of it is given in Part 5, Sec. 4, page 470.


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