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Chapter 5 The DEC PDP-8 123

binary arithmetic: two's complement add to the accumulator/tad

binary boolean: and to the accumulator/and

program control: jump/set program counter/jmp

jump to subroutine/jms

index memory and skip if results are zero/isz

Note that the add instruction, tad, is used for both data transmission and arithmetic.

The subroutine-calling instruction, jms, provides a method for transferring a link to the beginning (or head) of the subroutine. In this way arguments can be accessed indirectly, and a return is executed by a jump indirect instruction to the location storing the returned address. This straightforward subroutine-call mechanism, although inexpensive to implement, requires reentrant and recursive subroutine calls to be interpreted by software, rather than by hardware. A stack, as in the DEC 338 (Chap. 25), would be nicer.

The input_ output instruction/iot (:= op = 6) uses the remaining 9 bits of the instruction to specify instructions to input/ output devices. The 6 io_ select bits select 1 of 64 devices. The 3 bits, io_ p1_ bit, io_ p2_ bit, io_ p4_ bit, command the selected device by conditionally providing three pulses in sequence. The instructions to a typical io device are:

io_ p1_ bit ® (IO_ skip_ flag[io select] ® (PC PC + 1)) testing a condition of an 10 device output to a device input from a device

io_ p4_ bit ® (Output_ data[io select] AC)

io_ p2_ bit ® (AC Input_ data[io select])

There are three microcoded instruction groups selected by op = 7. The instruction decoding diagram (Fig. 2) and the ISP description (Appendix 1 of this chapter) show the microinstructions which can be combined in a single instruction. These instructions are: operate group 1 (: = (op = 7) L Ø iá 3ñ ) for operating on the processor state; operate group 2 (: = (op = 7) L (iá 3,11ñ = 102)) for testing the processor state; and the extended arithmetic element group (: = ((op = 7) L (iá 3,11ñ = 112))) for multiply, divide, etc. Within each instruction the remaining bits, á 4:10ñ or á 4:11ñ , are extended instruction (or opcode) bits; that is, the bits are microcoded to select instructions. In this way an instruction is actually programmed (or microcoded). For example, the instruction set_ link ® L 1 is formed by coding the two microinstructions, clear link, next, complement link.

opr_ 1® (iá 5ñ ® L¬ 0: next

iá 7ñ ® L ¬ Ø L)

Thus, in operate group 1, the instructions clear link, complement link, and set link are formed by coding instructioná 5,7ñ = 10, 01, and 11, respectively. The operate group 2 instruction is used for testing the condition of the Pc state. This instruction uses bits 5, 6, and 8 to code tests for the accumulator. The AC skip conditions are coded (0 ~ 7) as never, always, =0, ¹ 0, <0, ³ 0, £ 0, and >0. If all the nonredundant and useful variations in the two operate groups were available as separate instructions in the manner of the first seven (dca, tad, etc.), there would be approximately 7 + 12(opr_ 1) + 10(opr_ 2) + 6(EAE) = 35 instructions in the PDP-8.

The optional Extended Arithmetic Element/EAE includes additional Multiplier Quotient/MQ and Shift Counter/SC registers and provides the hardwired operations multiply, divide, logical shift left, arithmetic shift, and normalize. The EAE is defined on the last page of Appendix 1.

The interrupt scheme

External conditions in the input/output devices can request that Pc be interrupted. Interrupts are allowed if (Interrupt....state = 1). A request to interrupt clears Interrupt_ state (Interrupt_ state ¬ 0), and Pc behaves as though a jump to subroutine 0 instruction, jms 0, had been given. A special iot instruction (instruction = 60018) followed by a jump to subroutine indirect to 0 instruction (instruction = 52008) returns Pc to the interruptable state with Interrupt_ state = 1. The program time to save M(processor state/ps) is 6 Mp accesses (9 microseconds), and the time to restore Mps is 9 Mp accesses (13.5 microseconds).

Only one interrupt level is provided in the hardware. If multiple priority levels are desired, programmed polling is required. Most io devices have to interrupt because they do not have a program-controlled enable switch for the interrupt. For multiple devices approximately 3 cycles (4.5 m s) are required to poll each interrupter.

PMS structure

The PMS structure of the LINC-8-338 consisting of a Pc('LINC), Pc('PDP-8), and P.display('338) is shown in Fig. 1. The PDP-8 is just a single Pc. The Pc('LINC) is a very capable Pc with more

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