A MINICOMPUTER-COMPATIBLE MICROCOMPUTER SYSTEM: THE DEC LSI-11 305
contain the PDP-l1 program counter (PC) and stack pointer (SP), since they provide special processor functions and are accessed very frequently. The 5 remaining pairs of directly ad dressed registers are used for microprogram workspace, and normally contain the following: (1) the PDP-l1 macroinstruction, (2) the bus address, (3) the source operand. (4) the destination operand, and (5) the macro PSW and other status information.
The 8-bit ALU operates on two operands addressed by the microinstruction. When a full-word operation is specified, the data path is cycled twice, with the low order bit of each register address complemented during the second cycle. Thus a 16-bit macrolevel register is realized by two consecutive 8-bit registers in the register file. An 8-bit operand may also be sign- extended and used in a 16-bit operation, or an 8-bit literal value from the microinstruction may be used as one of the operands.
In addition to the register file and ALU, the data chip contains storage for several condition codes. These include flags for zero or negative results, as well as for carry or overflow; 4- or 8- bit carry flags are also provided for use in decimal arithmetic. Special flag-testing circuitry is also provided for efficiency in executing PDP-11 conditional branch instructions.
The Control Chip. The control chip generates MICROM addresses and control signals for external I/O operations. It contains an 11- bit location counter (LC), which is normally incremented after each MICROM access. The LC may also be loaded by "jump" instructions, or by the output of the programmable translation array. A one level subroutine capability is also provided by an 11-bit return register (RR), which may be used to save or restore the LC contents.
The programmable translation array (PTA), the heart of the control chip, consists of two programmable logic arrays (PLAs); the PTA generates new LC addresses which are a function of the microprocessor state and of external signals. Included in the microprocessor state is the 16-bit macroinstruction currently being interpreted; in this way, much of the macro- machine emulation may be done with the high efficiency provided by the PTA. The combinational logic of the two PLAs allows the PTA to arbitrate interrupt priorities, translate macroinstructions, and, in general. to replace the conventional "branch-on-microtest" micro- primitive. Since the microlocation counter is one of the PTA inputs, it is normally unnecessary to specify explicitly the desired translation or multiway branch; this information is implicit in the address of the microinstruction which invokes the PTA. External condition handling is made possible by four microlevel interrupt lines which are input to the PTA. Also feeding the PTA are three internal status flags which are set and reset under microprogram control.
The MICROM Chip. The micro read-only memory, or MICROM, serves as the control store for the microprocessor. The micro instruction width is 22 bits. Sixteen of these bits comprise the traditional microinstruction; one is used to latch a subroutine return address, and one to invoke programmed translations; the remaining four bits (which drive TTL-compatible outputs) perform special system-defined functions.
Each MICROM chip contains 512 words, or one-fourth of the 2 K microaddress space. Proper "chip-select" decode is accomplished by masking a 2-bit select code (along with the microcode) into each MICROM at the time of manufacture; no external selection logic is required.
The Microinstruction Bus. As seen in Figure 2, microinstructions and microaddresses share the microinstruction bus lines (MIB 00:21). Instructions thus fetched are executed by the data chip while the next microaddress is computed by the control chip. The bus design, then, allows fully pipelined microinstruction execution, with data and control operations over lapped.