CDC 6600 registers
The processor state consisted of 3 groups of highly functional registers: of the eight 18-bit registers for memory access, 6 control loads, and 2 control stores to the corresponding eight 60-bit floating point registers; and there are eight 18-bit registers for integer and indexing operations. Operations could be carried out simultaneously on multiple registers in each group as long as there was no data interlock.
Data trunks carried information from registers to memory and to the functional units.
Of the functional units, 4 are for carrying out 60-bit floating point arithmetic among the 8 X registers. The other 6 carry out logic, indexing, and program control on the address, A and increment / index, B registers.
The control for managing the parallelism and interlocking was handled in two units called the stunt box and Scoreboard.
Instruction parallelism comes from an 8 word stack.