784 Part 4½ Family Range, Compatibility, and Evolution Section 2½ Minicomputer Families
 
 

PDP-11/20, gate density has not improved markedly. Speed improvement has taken place in the Schottky TTL, and a speed/power improvement has occurred in the low power Schottky (LS) series. Departures from medium-scale integrated transistor-transistor logic, in terms of gate density, have been few, but effective. Examples are the hit-slice in the PDP-11/34 Floating-Point Processor, the use of programmable logic arrays in the PDP-11!04 and PDP-11/34 control units, and the use of emitter-coupled logic in some clock circuitry.

Memory densities and costs have improved rapidly since 1969 and have thus had the most impact. Read-write memory chips have gone from 16 bits to 4,096 bits in density and read-only memories from 16 hits to the 8 or 16 Kbits widely available in 1978.

The memory technology of 1969 imposed several constraints. First, core memory was cost-effective for the primary (program) memory, hut a clear trend toward semiconductor primary memory was visible. Second, since the largest high speed read-write memories available were just 16 words, the number of processor registers had to be kept small. Third, there were no large high speed read-only memories that would have permitted a microprogrammed approach to the processor design.

These constraints established four design attitudes toward the PDP-11's architecture. First, it should he asynchronous, and thereby capable of accepting different configurations of memory that operate at different speeds. Second, it should be expandable to take eventual advantage of a larger number of registers, both user registers for new data-types and internal registers for improved context switching, memory mapping, and protected multiprogramming. Third, it could be relatively complex, so that a microcode approach could eventually be used to advantage: new data-types could be added to the instruction set to increase performance, even though they might add complexity. Fourth, the Unibus width should be relatively large, to get as much performance as possible, since the amount of computation possible per memory cycle was relatively small.

As semiconductor memory of varying price and performance became available, it was used to trade cost for performance across a reasonably wide range of PDP-11 models. Different techniques

were used on different models to provide the range. These techniques include: microprogramming for all models except the 11/20 to lower cost and enhance performance with more data-types (for example, faster floating point); use of faster program memories for brute-force speed improvements (e.g., 11/45 with MOS primary memory, 11/55 with bipolar primary memory, and the 11/60 with a large writable control store); use of caches (11/70, 11/60, and 11/34C); and expanded use of fast registers inside the processor (the 11/45 and above). The use of semiconductors versus cores for primary memory is a purely economic consideration.

Table 2 shows characteristics of each of the PDP-11 models along with the techniques used to span a range of cost and performance. (Chapter 39 gives a detailed comparison of the processors.) Figure 2 gives the cost/performance mapping for the various PDP-11 implementations.
 

References

Bell et al. [1970]; Eckhouse [1975]; Gear [1974]; Shannon [1948]; Stone and Siewiorek [1975].