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674 Part 3 Computer Classes
Section 3 Minicomputers

 

Table 1 Average PDP-1 1 Instruction Execution Times in Microseconds

Fetch

Source

Destination

Execute

Total

Speed relative to LSI-11

LSI-l 1

2.514

0.689

1.360

1.320

5.883

1.000

PDP-11/04

1.940

0.610

0.811

0.682

4.043

1.455

PDP-11/10

1.500

0.573

0.929

1.094

4.096

1.436

PDP-11/20

1.490

0.468

0.802

0.768

3.529

1.667

PDP-11/34

1.630

0.397

0.538

0.464

3.029

1.942

PDP-11/40

0.958

0.260

0.294

0.575

2.087

2.819

PDP-11/45 (bipolar memory)

0.363

0.101

0.213

0.185

0.863

6.820

PDP-11/60 (87% cache hit ratio)

0.541

0.185

0.218

0.635

1.578

3.727

 

The choice of these two factors is motivated by their dominant contribution to, and (approximately) linear relationship with, performance. Keeping the number of independent variables low is also important because of the small number of data points being fitted to the model.

The model itself is of the form:

ti = k1c1i + k2c2i

where ti = the average instruction execution time of machine i from Table 1

c1i = the microcycle time of machine i (for machine with selectable microcycle times, the predominant time is used)

c2i = the memory-read-pause time of machine

This model is only an approximation, since it assumes k1 and k2 will be constant over all machines. In general this will not be the case. k1 is the number of microcycles expected in a canonical instruction. This number will be a function mainly of data-path connectivity, and strictly speaking, another factor should be included to take that variability into account; however, since the data-path organizations of all PDP- 11 implementations considered here (except the 11/03, 11/45, and 11/60) are quite comparable, the simplifying assumption of calling them all identical at the price of explaining somewhat less of the variance shall be made. k2 is the number of memory accesses expected in a canonical instruction and also exhibits some variability from machine to machine. A small part of this is due to the fact that some PDP-11's actually take more memory cycles to perform a given instruction than do others (this is really only a factor in certain 11/10 instructions, notably JMP and JSR, and the 11/20 MOV instruction). A more important source of variability is the Unibus-processor overlap logic incorporated into some PDP-11 implementations, which effectively reduces the actual contribution of the k2c2i term by overlapping more memory access time with processor operation than is excluded from the memory-read-pause time.

Given the model and the dependent and independent data for each machine as given in Table 2, a linear regression was applied to determine the coefficients k1 and k2 and to find out how much of the variance is explained by the model.

If the regression is applied over all eight processors, k1 = 11.580, k2 = 1.162, and R2 0.904. R2 is the amount of variance accounted for by the model, or 90.4 percent. If the regression is applied to just the six midrange processors, k1 = 10.896, k2 = 1.194, and R2 = 0.962. R2 increases to 96.2 percent partly because fewer data points are being fitted to the model and partly because the LSI-11 and 11/45 can be expected to have different k coefficients from those of the midrange machines and hence do not fit the model as well. Note that if two midrange machines, the 11/04 and the 11/40, are eliminated instead of the LSI-11 and 11/45, then R2 decreases to 89.3 percent rather than increasing. The k coefficients are close to what should be expected for average microcycle and memory cycle counts. Since k1 is much larger than


Table 2 Top-Down Model Parameters in Microseconds

Independent variables

Dependent variable

Microcycle time

Memory- read- pause- time

Average instruction execution time

LSI-11

0.400

0.400

5.883

PDP-11/04

0.260

0.940

4.043

PDP-11/10

0.300

0.600

4.096

PDP-11/20

0.280

0.370

3.529

PDP-11/34

0.180

0.940

3.029

PDP-11/40

0.140

0.500

2.087

PDP-11/45 (bipolar memory)

0.150

0.000

0.863

PDP-11/60 (87% cache hit ratio)

0.170

0.140

1.578

 

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