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Chapter 38

A New Architecture for Mini-Computers: The DEC PDP-111

G. Bell / R. Cady / H. McFarland / B. DeLagi / J. O'Laughlin / R. Noonan / W. Wulf


The mini-computer2 has a wide variety of uses: communications controller; instrument controller; large-system pre-processor; real-time data acquisition systems . . . ; desk calculator. Historically, Digital Equipment Corporation's PDP-8 Family, with 6,000 installations has been the archetype of these mini-computers.

In some applications current mini-computers have limitations. These limitations show up when the scope of their initial task is increased (e.g., using a higher level language, or processing more variables). Increasing the scope of the task generally requires the use of more comprehensive executives and system control programs, hence larger memories and more processing. This larger system tends to be at the limit of current mini-computer capability, thus the user receives diminishing returns with respect to memory, speed efficiency and program development time. This limitation is not surprising since the basic architectural concepts for current mini-computers were formed in the early 1960's. First, the design was constrained by cost, resulting in rather simple processor logic and register configurations. Second, application experience was not available. For example, the early constraints often created computing designs with what we now consider weaknesses:

1 Limited addressing capability, particularly of larger core sizes

2 Few registers, general registers, accumulators, index registers, base registers

3 No hardware stack facilities

4 Limited priority interrupt structures, and thus slow context switching among multiple programs (tasks)

5 No byte string handling

6 No read only memory facilities

7 Very elementary I/O processing

8 No larger model computer, once a user outgrows a particular model

9 High programming costs because users program in machine language.

In developing a new computer the architecture should at least solve the above problems. Fortunately, in the late 1960's integrated circuit semiconductor technology became available so that newer computers could be designed which solve these problems at low cost. Also, by 1970 application experience was available to influence the design. The new architecture should thus lower programming cost while maintaining the low hardware cost of mini-computers.

The DEC PDP-11, Model 20 is the first computer of a computer family designed to span a range of functions and performance. The Model 20 is specifically discussed, although design guidelines are presented for other members of the family. The Model 20 would nominally be classified as a third generation (integrated circuits), 16-bit word, 1 central processor with eight 16-bit general registers, using two's complement arithmetic and addressing up to 216 eight bit bytes of primary memory (core). Though classified as a general register processor, the operand accessing mechanism allows it to perform equally well as a 0-(stack), 1-(general register) and 2-(memory-to-memory) address computer. The computer's components (processor, memories, controls, terminals) are connected via a single switch, called the Unibus.

1AFIPS Proc. SJCC, 1970, pp. 657-675.

2The PDP-11 design is predicated on being a member of one (or more) of the micro, midi, mini, . . . , maxi (computer name) markets. We will define these names as belonging to computers of the third generation (integrated circuit to medium scale integrated circuit technology), having a core memory with cycle time of .5 ~ 2 microseconds, a clock rate of 5 ~ 10Mhz . . . , a single processor with interrupts and usually applied to doing a particular task (e.g., controlling a memory or communications lines, pre-processing for a larger system, process control). The specialized names are defined as follows:

Maximum addressable primary memory (words)

Processor and memory cost (1970 kilodollars)

Word length (bits)

Processor state (words)

Data types


8 K

~ 5

8 ~ 12


Integers, words, boolean vectors



5 ~ 10

12 ~16


Vectors (i.e., indexing)


65 ~ 128 K

10 ~ 20

16 ~ 24


Double length floating point (occasionally)


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