C:\BELLBOOK\P001-100\HTMFILES\CSP0599.HTM

Section 1 ½ Monolithic Microcomputers 583

Table 1 (Continued)

TMS0980	TMS1980	TMS0920	TMS1990	TMS1500	TP0310	TP0320
PMOS	PMOS	PMOS	PMOS	PMOS	CMOS	CMOS
28	28	28	28	28	28	28
4 bits	4 bits	40 bits serially	4 bits	64 bits serially	40 bits serially	4 bits
2048´ 9 bits	2048´ 9 bits	511´ `9 bits`	1024´ `8` bits	2048´ 13 bits	511´ `9 bits`	2048´ `9 bits`
`64´ 9 bits`	`64´ 9 bits`	`40´ 5 bits`	`64x 4 bits`	`64´ 20 bits`	`40´ 5 bits`	`64´ 13 bits`
9	10	30	12	165	30	11
46	47	. . . . . .	31	. . . . . . .	. . . . . . . .	46
VLED	VF	VF	VLED	VLED	LC	LC
TI-30 Slide Rule Business, analytical, financial 6/76 Programmers Number base conversion 8/77	Dataman Mathematical drills 6/77 TI-1050 5-function 6/77	TI-1025 4-function 6/ 77 TI-1050 5-function 6/77	TI-1000 4-function 6/77	TI-57 Scientific programmable4/77 MBA Financial, statistical 8/77 TI-55 Scientific programmable 1/78	TI-1030 4-function 6/78	TI-50 Scientific 6/78 BAII Financial 6/78

instruction. Thus, a preloaded register pair (x,y) is assumed to contain the currently valid address when executing the memory-reference instruction. The register can be updated by using instructions with immediate operands or by incrementing. (Note that the x and y registers are physically separated so that a carry from the y register does not change x. x would have to be changed under programmed control.) This mechanism has also been used on microcomputers (e.g., Intel 8008 and 8080).

Program Counter (PC) incrementing. In order to save a separate incrementer for the PC or trips through the ALU for updating, the PC update is implemented by a pseudo-random sequence to go through all 64 states produced by a feedback shift register such as is used in cyclic redundancy codes. Thus only a shifter and several logic gates are required. Figure 1 gives the logic implementation for the feedback shift counter.

Instructions with side effects. Certain instruction op codes have been selected so that they can apply appropriate constants to the ALU and RAM. While this saves ROM space for frequently used constants, it seems to make op code selection difficult and add nonsymmetry to the instruction format.

The TMS1000 was introduced in 1974 and used in the SR-16 calculator. Table 1 summarizes the 13 different chips used in TI single-chip calculators. These chips vary in implementation technology, number of I/O lines, display drive, amount of ROM (up to 26.6 Kbit) and amount of RAM (up to 1280 bits). Calculator applications range from simple four-function calculators to the 50-step programmable TI-57. As of mid 1979, over 35 million TMS 1000 chips were used in both calculator and noncalculator applications, establishing the TMS1000 as the computer

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