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450 Part 2 ½ Regions of Computer Space Section 6½ Fault-Tolerant Systems
 

Hardware System Organization

The block diagram of the STAR computer is shown in Fig. 2. Communication between the units is carried out on two four-wire buses: the memory-out (M-O) bus, and the memory-in (M-I) bus. The abbreviations designate the following units.
 
COP Control processor, contains the location counter and index registers and performs modification of instruction addresses before execution
LOP Logic processor, performs logical operations on data words (two copies are powered).
MAP Main arithmetic processor, performs arithmetic operations on data words.
ROM READ-ONLY memory, 16,384 permanently stored words.
RWM READ-WRITE memory unit with 4096 words of storage (at least two copies powered; 12 units are directly addressable).
IOP Input/output processor, contains I/O buffer registers.
IRP Interrupt processor, handles interrupt requests.
TARP Test and repair processor, monitors the operation of the computer and implements recovery (three copies are powered).

The functional units (processors and memories) of the STAR computer communicate by means of the M-I and M-O (four-wire) information buses. The 32-bit words are transmitted on these two buses as eight bytes of four bits each. Three control signals are sent from the TARP on the three-wire control bus to synchronize the operations of the functional units and to initiate recovery. Otherwise the functional units operate autonomously. Unless otherwise noted, one copy of each unit is powered at a given time. The decentralized organization allows a standard interface between each unit and the remainder of the computer. Each STAR unit interfaces with the computer by the means of 14 signal lines. Eleven lines, both in active and spare units, are permanently connected to the computer system buses, and three are connected

to the TARP array. An unpowered unit cannot produce logic one outputs. The external connections of a STAR unit are shown in Fig. 3.

The four input and four output lines are connected to the data M-I and M-O buses. They receive and send coded machine words in four-bit bytes. The power switch control input causes power to be applied to the unit. The three control bus input signals are: CLOCK, a basic timing input: SYNC, a periodic synchronization signal; and RESET, a signal that forces the unit into a standard initial state. Two unit status lines send information on the internal operation of the unit to the TARP. These lines carry multiplexed information which will be discussed in a following section. Each functional unit is autonomous and contains its own sequence generator as well as storage for the current operation code, operands, and results. The internal design of a unit may be altered without affecting other units as long as the interface specifications are observed.

It is to be noted that the IOP and IRP units are shown combined in Fig. 2.

Standard Operation

The STAR computer has two modes of operation: the standard mode and the recovery mode (under TARP control). During the standard mode the stored programs are carried out. The TARP processor issues the principal CLOCK signal and SYNC signal which occurs when a new step is initiated in the execution of an instruction. Ten CLOCK periods form the basic time unit (cycle) of the computer. During the first period, a four-bit "step-code" (in 2-out-of-4 encoding) is issued by the TARP to the M-O bus. The next eight periods are employed to transmit or manipulate one eight-byte machine word. During the tenth period a four-bit "condition-code" byte may be broadcast by one of the functional units. The ten-period cycle is needed because of the series-parallel organization of the computer.

One instruction is executed in two or three steps. In the first step, the address of the instruction is sent from the location

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