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Section 3 ½ Concurrency: Single-Processor System 275

(b) Double precision (8 bit exponent; 56 bit mantissa)

DADF

DSBF

DMPF

DDVF

DSQRTF

ADD ARRAY FIELD TO ARRAY FIELD

SUBTRACT ARRAY FIELD FROM ARRAY FIELD

MULTIPLY ARRAY FIELD BY ARRAY FIELD

DIVIDE ARRAY FIELD BY ARRAY FIELD

CALCULATE SQUARE ROOT OF ARRAY FIELD

G. Miscellaneous parallel array instructions

FIND

STEP RESVFST COUNTRS

SHIFTY ROTATY

FIND FIRST RESPONDER(Y RESPONSE STORE BITS SET)

STEP TO FIRST RESPONDER AND CLEAR IT
STEP TO FIRST RESPONDER AND CLEAR ALL OTHERS
COUNT RESPONDERS

SHIFT Y END-OFF (OPTIONAL Pio REQUIRED)
ROTATE Y END-AROUND (OPTIONAL Pio REQUIRED)

VI. Control and Test instructions

INT ILOCK

WAIT RUN

RUNBF

IOWAIT

INSTP

EXIT

CONTROL AND TEST INTERRUPT
CONTROL AND TEST INTERLOCK

DEACTIVATE AP
START LOADING OVERLAY MODULE

IDENTIFY OVERLAY MODULE

WAIT OR BRANCH IF I/O IS BUSY

INTERRUPT SEQUENTIAL PROCESSOR PROGRAM

TRANSFER CONTROL TO BATCH OPERATING SYSTEM (BOS)

VII. Input/Output (I/O) instructions

A. Standard I/O instructions

OPEN

OBUFF

READ

RBUFF

WRITE WBUFF CLOSE

INITIALIZE DATASET

DEFINE I/O DATASET

START READING

DEFINE INPUT BUFFER

START WRITING
DEFINE OUTPUT BUFFER
RELEASE DATASET

B. Optional parallel I/O (Pio) instructions

TPIO MAM SAM LAM DPIO

CONTROL AND TEST Pio CONTROL
MOVE DATA FROM ARRAY TO ARRAY
STORE DATA FROM ARRAY INTO AP CONTROL MEMORY
LOAD DATA IN ARRAY FROM AP CONTROL MEMORY
DEFINE Pio MOVE, STORE, OR LOAD

VIII. Program pager instructions

STRTSG ENDSG MVSG MVSGI PAGER

START PAGE SEGMENT
END PAGE SEGMENT
MOVE PAGE SEGMENT
MOVE PAGE SEGMENT IMMEDIATELY
CONTROL AND TEST PROGRAM PAGER

 

As of January 1979, five STARANs have been built. A listing of the configuration of existing STARAN systems is given in Table 8. All STARAN systems include one AP array, AP control, control


Table 8 STARAN Configuration

System

Series

Arrays

Pio

Comments

1

B

4

Yes

2

B

4

Yes

Parallel-head disk

3

B

2

No

4

B

2

No

Multiple tape units

5

E

4

No

Cross bar I/0 to array


B arrays are 256 PEs by 256 bits.
E arrays are 256 PEs by 9,216 bits.

memory, program pager, sequential controller, disk, line printer, card reader, and control terminal.

 

References

Barnes, Brown, Kato, Kuck, Slotnick, and Stokes [1968]; Batcher [1976]; Batcher [1977]; Boulis and Faiss [1977]; Falk [1976]; Feierbach and Stevenson [1979]; Flynn [1966], Gregory and McReynolds [1963]; Keller [1975]; Kuck [1968]; Lunde [1977]; Ramamoorthy and Li [1977]; Ruben, Faiss, Lyon, and Quinn [1976]; Slotnick et al. [1962]; Thurber and Wald [1975]; Vocar and Faiss [1977]; Yau and Fung [1977].

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