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272 Part 2½ Regions of Computer Space
Section 3 ½ Concurrency: Single-Processor System


Table 5 Performance Comparison of STARAN B versus Conventional Computer Systems

Project

STARAN time (ts)

Conventional computer time (tc)

Ratio (tc /ts)

LACIE

Classification Clustering

8.0 mina 0.62 mina

(360/75) 210 mina (360/75) 35 mina

26
56

427 SPACE COMPUTATION COMPLEX

SPG4 algorithm

Worst case (512 objects) Best case (1536 objects)

451 msb 180 msb

(H6080) 1280 msb (H6080) 7680 msb

2.8
42.7

Digital photogrammetry

Map production Stereo correlation

3.4 mm 1.47 hc

(CDC 6400) 75 min (CDC 6600) 12.0 hc

22.1 8.1

SACWARDANS (data mgt.)

Minimum load Maximum load

9.54 mind 1.32 hd

(H6080) 227.4 mind (H6080) 83.19 hd

23.8 63.0

Image averaging process

0.17 s 0.17 s

(360/195) 8.04 se (360/65) 60.0 se

47.3
353

aNASA data (Large Area Crop Inventory Experiment)

b Mitre data

cArmy ETL data

dAF and PRC data (based on H6080 enhancement with STARAN, STARAN also results in 3 to 1 file reduction)
eU.S. government data


STARAN B has been programmed for two general types of application [Boulis, 1977]: bit-manipulation tasks (e.g., data base management, text searching, command and control, and air traffic control) and bit-group-manipulation tasks (e.g., image process-


Table 6 Comparison of Staran Models B and E

Feature

STARAN B

STARAN E

Memory

Page memory

Size Speed

512-1024 words 200 ns

4096-8192 words
100ns

High-speed data buffers

Size

512-1024 words

512-8192 words

Associative modules

Number of modules Number of PEs Memory array Number of arrays per module Instruction execution speed

1:32 256:8192 256 by 256 1
120 ns

1:8
256:2048
256 by 256
9:256
100 ns

ing, signal processing, weather forecasting, reactor design, and fluid dynamics applications). STARAN B applications have been measured at 20 MOPs (million operations per second) using two arrays in an image-processing application [Vocar; 1977]. Table 5 illustrates the type of performance encountered over a range of applications.

The advent of larger memory chips provided the reason for reimplementation of the architecture as STARAN E. At the same time, some of the architectural shortcomings of the STARAN B were corrected. These modifications included longer word length (up to 65 kilobits), higher transfer rate between array and control memory (via an eight-port crossbar switch that allows for cycle- steal memory access among the AMs and between AMs and external devices), and larger page-memory sizes. Table 6 highlights the major differences between the STARAN B and the STARAN E. Whereas STARAN B could execute a 1,024-point 16-bit real FFT in 3 ms, STARAN E requires only 0.6 ms.

Software primarily consists of a macro assembler, a linker, a loader, and debugging aids. Macros are provided for the common vector operations (e.g., FMPF, multiply array field by array field) so that the applications programmer does not deal with the bit-serial level of detail. Table 7 lists the STARAN instruction and macro instruction sets.

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