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Section 3 Concurrency: Single-Processor System 261

point in memory. Resolution of the identity of the interrupting I/O device is through polling.


A critical measure of performance is interrupt response time, the time between an I/O device's requesting the attention of the Pc by posting an interrupt and the Pc's executing the first instruction of a program to service that I/O device. The selection of the interrupt scheme to employ in a computer is a function of a cost/response-time tradeoff. If response time is critical, computer implementations contain several register sets selectable by the interrupt scheme. Thus the time to switch the context (i.e., the state of the interrupted program) under program control is significantly reduced.

Processor-Memory

Another area of overlap in the traditional machine is between the processor and memory. For any given technology, memory speed is less than that of processor speed. This is partly due to the delays in accessing a word from a large memory array and partly to delays imposed by the processor-memory bus protocol. Thus ways have been developed to cut down memory-to-processor delays. Many of these schemes are based on using a memory that is of multiple word width (e.g., 2 words or 4).

One mechanism is to prefetch instructions so that the next instruction is available as soon as the processor is ready. Prefetching is implemented by fetching a block of instructions and storing them in an instruction buffer. The block can be transferred simultaneously (see the subsection Memory below) or sequentially (the next sequential instruction is fetched during the execution of the current instruction). In an n-instruction buffer, a block of instructions is kept in the local instruction buffer. Table 2 depicts

 

Table 2 Concurrency in Machines Treated in This Book

Overlap

Processor-I/O

Processor-memory

Processor

Memory

Parallelism

IBM S/360-91

Interrupts

Instruction prefetch : eight 64-bit words

10-or more-stage pipe 3 arithmetic units

16-way interleaving 64-bit word access

Parallel by word
Asynchronous multiple function units

CDC 6600

Interrupts in peripheral processing units

Instruction prefetch: eight 60-bit words

10 arithmetic units

32-way interleaving 60-bit word access

Parallel by word
Multiple control units
Asynchronous multiple function units

STARAN

Interrupts

User-controlled page loading: 512-4096 32-bit words

3-stage pipe

Separate data and
instruction memories 5-way interleaving
32-bit word access

Serial by bit

Parallel by bit slice

TI ASC

Interrupts

Instruction prefetch: eight 32-bit words Operand prefetch: eight 32-bit words

4-stage pipe for instructions 8-stage pipes for arithmetic units

8-way interleaving 256-bit word access

Parallel by word

Multiple control units

Iliac IV

Interrupts

Instruction prefetch : eight 64-bit words

2-stage fetch/execute pipe

8-way interleaving 512-bit word access

Separate data and Parallel by word instruction memories 64 lockstep functional units

CRAY-1

Interrupts

Instruction prefetch : 64 16-bit words

12 arithmetic units

16-way interleaving 64-bit word access

Parallel by word
Multiple control units

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