188 Part 2 ½ Regions of Computer Space Section 1 ½ Microprogram-Based Processors
 

Table 1 ALU Operand Sources
 

-EA	I0	-OEB	ALU operand R	ALU operand S
L	L	L	RAM output A	RAM output B
L	L	H	RAM output A	DB0-3
L	H	X	RAM output A	Q Register
H	L	L	DA0-3	RAM output B
H	L	H	DA0-3	DB1-3
H	H	X	DA0-3	Q Register

L = LOW H =HIGH X = don't care

ALU Shifter

Under instruction control, the ALU shifter passes the ALU output (F) non-shifted, shifts it up one bit position (2F), or shifts it down one bit position (F/2). Both arithmetic and logical shift operations are possible. An arithmetic shift operation shifts data around the most significant (sign) bit position of the most significant slice, and a logical shift operation shifts data through this bit position (see Fig. 2). SIO₀ and SIO₃ are bidirectional serial shift inputs/outputs. During a shift-up operation, SIO₀ is generally a serial shift input

Table 2 ALU Functions
 

I4	I3	I2	I1	Hex code	ALU functions
L	L	L	L	0	I0 = H	Fi = HIGH
					I0 = L	Special functions
L	L	L	H	1	F = S Minus R Minus 1 Plus Cn
L	L	H	L	2	F = R Minus S Minus 1 Plus Cn
L	L	H	H	3	F = R Plus S Plus Cn
L	H	L	L	4	F = S Plus Cn
L	H	L	H	5	F = -S Plus Cn
L	H	H	L	6	F = R Plus Cn
L	H	H	H	7	F = -R Plus Cn
H	L	L	L	8	Fi = LOW
H	L	L	H	9	Fi = Ri AND Si
H	L	H	L	A	Fi = Ri Exclusive-N0R Si
H	L	H	H	B	Fi = Ri Exclusive-OR Si
H	H	L	L	C	Fi = Ri AND Si
H	H	L	H	D	Fi = Ri NOR Si
H	H	H	L	E	Fi = Ri NAND Si
H	H	H	H	F	Fi = Ri 0R Si

L=LOW H=HIGH i= 0 to 3

and SIO₃ a serial shift output. During a shift down operation, SIO₃ is generally a serial shift input and SIO₀ a serial shift output.

To some extent, the meaning of the SIO₀ and SIO₃ signals is instruction-dependent. Refer to Tables 3 and 4 for an exact definition of these pins.

The ALU shifter also provides the capability to sign-extend at slice boundaries. Under instruction control, the SIO₀ (sign) input can be extended through Y₀, Y₁, Y₂, and Y₃ and propagated to the SIO₃ output.

A cascadable 5-bit parity generator/checker is designed into the Am2903 ALU shifter and provides ALU error detection capability. Parity for the F₀, F₁, F₂, and F₃ ALU outputs and SIO₃ input is generated and, under instruction control, is made available at the SIO₀ output.

The instruction inputs determine the ALU shifter operation. Table 4 defines the special functions and the operation the ALU shifter performs for each. When the Am2903 executes instructions other than the nine special functions, the ALU shifter operation is determined by instruction bits I₈I₇I₆I₅. Table 3 defines the ALU shifter operation as a function of these four bits.

Q Register

The Q register is an auxiliary 4-bit register. It is intended primarily for use in multiplication and division operations; however, it can also be used as an accumulator or holding register for some applications. The ALU output, F, can be loaded into the Q register, and/or the Q register can be selected as the source for the ALU S operand. The shifter at the input to the Q register provides the capability to shift the Q-register contents up one bit position (2Q) or down one bit position (Q/2). Only logical shifts are performed. QIO₀ and QIO₃ are bidirectional shift serial inputs/outputs. During a Q-register shift-up operation, QIO₀ is a serial shift input and QIO₃ is a serial shift output. During a shift-down operation, QIO₃ is a serial shift input and QIO₀ is a serial shift output.