**148 Part 1 ½ Fundamentals Section
3 ½ Computers of Historical Significance**

there are several stacks instructions and operands are separated wherever possible. Under these conditions it is possible to calculate the limit imposed on the operating speed by the cycle time for different divisions of the core store. The results are shown in Fig. 8; for stacks arranged in pairs instructions are read in pairs and in all cases both instructions and operands are assumed to be on the core store. Operands are assumed to be selected at random from the operand space; for instance, in the case of two stacks arranged as a pair, successive operand requests have equal probability of belonging to the same stack or to alternate stacks.

The limit imposed by a four stack store is never severe compared with
other limitations; for example, the sequence of floating point addition
orders discussed in Sec. 4 required 1.6m sec
per order with ideal distribution of instructions and operands. Division
into eight stacks, although it reduces the limit, will not have an equivalent
effect on the over-all operating speed, and such a division was not considered
to be justified.

**References**

Kilburn, Edwards, Lanigan, and Sumner [1962]; Brooker [1960]; Edwards,
Lanigan, and Kilburn [1960]; Kilburn, Edwards, and Thomas [1956]; Kilburn,
Edwards, and Aspinall [1960]; Kilburn and Grimsdale [1960]; Kilburn, Howarth,
Payne, and Sumner [1961]; Lonsdale and Warburton [1956]; Papian [1957];
Fotheringham [1961]; Hartley [1968]; Howarth [1963]; Howarth, Jones, and
Wyld [1962]; Howarth, Payne, and Sumner [1961); Morris, Sumner, and Wyld
[1967]; Sumner, Haley, and Chen [1962].