Chapter 8 ½Structural Levels of the PDP-8 115
and the INTERRUPT. ENABLE bit. The external processor state is composed of console switches and an interrupt request.
The instruction format can also be presented as a decoding diagram or tree (Fig. 5). Here, each block represents an encoding of bits in the instruction word. A decoding diagram allows one more descriptive dimension than the conventional, linear ISPS description, revealing the assignment of bits to the instruction. Figure 5 still requires ISPS descriptions for the memory, the processor state, the effective address calculation, the instruction interpreter, and the execution for each instruction. Diagrams such as Fig. 5 are useful in the ISP design to determine which instruction operation codes are to be assigned to names and operations, and which instructions are free to he assigned (or encoded).
There are eight basic instructions encoded by 3 opcode hits of the instruction register, that is, IR<0:2>. Each of the first memory reference six instructions, where the opcode is less than or equal to 5, has four addressing modes (direct page. zero, direct current. page, indirect page. zero, and indirect current. page). The first six instructions in the following four categories are:
"deposit and clear Accumulator" (DCA). (Note that the add instruction, TAD, is used for both data transmission and arithmetic.)
2 Binary arithmetic
"two's complement add to the Accumulator" (TAD).
3 Binary Boolean
"and to the Accumulator" (AND).