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24 Part 1½ Fundamentals Section 1½ Abstraction and Notation

The expression<> indicates a single, unnamed bit (L is only 1 bit long and there is no need to specify a name for it).

The program counter is used to store the address of the instruction currently being executed as the machine steps through a program:

PC\Program. Counter<0: 11>,

Twelve bits are needed in the PC to address all 4,096 locations of MP.

In the PDP-8 I/O devices are allowed to "interrupt" the central processor. When a device requires service from the central processor, it emulates a subroutine call, forcing the processor to execute an appropriate I/O subroutine. The presence of an interrupt request is indicated by setting the interrupt, request flag. The processor can honor these requests or not, depending on the setting of the interrupt, enable bit:

interrupt. enable<>,

interrupt. request<>,

There are 12 console switches which can be read by the processor. These switches are treated as a 12-bit register by the central processor:

switches<0: 11>,


Instruction Format

Like most data-types and registers on the PDP-8, instructions are 12 bits long:

i\instruction<0: 11>,

An instruction is a special kind of data-type. It is really an aggregate of smaller information units (operation codes, address modes, operand addresses, etc.). The structure of the instructions must be exposed by describing the format. Most PDP-8 instructions contain an operation code and an operand address:

op\operation. code<O :2> := i<0:2>, ib\indirect .bit<> := i<3>, pb\page .bit<> := I<4>, pa\page . address<O :6> := i<5: l1>,

The abstractions op, ib, pb, and pa allow the treatment of selected fields of the PDP-8 instructions as individual entities.

Partitioning the Description

In ISPS, a description can be divided into sections of the form:
**section. name** <declaration>, <declaration>,
**section name** <declaration>, <declaration>,

Each section begins with a header, an identifier enclosed between double asterisks. A section consists of a list of declarations separated by commas. Section names are not reserved keywords in the language but are used to convey some information about the entities declared inside the section. The register and memory declarations presented so far can be grouped into sections as shown at the top of page 25.

A few more field declarations have been added. These are used to interpret the I/O and operate instructions. The PDP-8 I/O instruction uses the nine bits of addressing information to specify operations for the I/O devices. These nine bits are divided into a device selector field (six bits, io. select<0:5>) and a device operation field (three hits, io.pulse<0:2>). Note that several alternate field declarations may he associated with the same portion of a register or data-type, thus adding flexibility to the description. A comment is indicated by an introductory exclamation point, and all characters following the exclamation point to the end of the line are treated as commentary and not as part of the description. The PDP-8 Operate instruction's address field is not interpreted as an address hut as a list of suboperations. The DEC PDP-8 processor manuals provide additional details.

Effective Address

The effective address computation is an algorithm which computes addresses of data and instructions:

**Effective . Address**

last .pc<0: 11>,

MA\effective .memory.address<O :11> :=

begin DECODE pb =>

begin 0 :=MA='OOO0O@pa, ! page zero 1 :=MA =last.pc<0:4>@pa !current page end next

IF not ib => LEAVE MA next IF MA<0 :8> eqv #001 =>

MP[MA] =MP[MA] +l next !auto index

MA = MP[MA] end,


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