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Chapter 1½ Computer Classes and Evolution 7
control pulses (example: direct I/O control by a
microcomputer).
Position 2 A simple controller (K) takes over the generation of the control pulse sequences upon central processor command. The central processor must periodically examine (poll) the controller to see when it has completed a command. The central processor and controller operate in parallel, allowing overlap between computations and I/O (example: Intel 4004). Position 3 Interrupts are added to the simple controller so that it can signal the central processor upon completion of a command. The central processor need not spend time polling the controller (example: most contemporary minicomputers and microcomputers). Position 4 Direct memory access (DMA) is added to the controller, so that the controller can move a block of data to or from memory without bothering the central processor. The central processor is interrupted only after the controller has completed the block move, not after each datum, as in position 3(example: PDP-II). Position 5 An instruction buffer is added to the controller so that the central processor can set up a sequence of I/O activities. The controller interrupts only after the entire sequence has been executed. Position 6 The controller is enhanced to contain a complete instruction set, including instructions for program control, looping, and testing. The central processor creates an I/O program in memory that the

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