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636 Appendix

4.3 Instruction Format. The instruction formats are usually declared in the same fashion as memory and are not distinguishable as special non-memory entities. Normally, the instructions are carried in registers; it is thus natural to give declarations in this fashion, Usually only a single declaration is made, the instruction/i, followed by the declarations of the parts of the instruction-the operation code, the address fields, indirect bit, etc.

EXAMPLE

i/instruction[0:4]á 0:7ñ

five 8 bit byte instruction

opá 0:4ñ : = i[0]á 0:4ñ

opcode

rá 0:15ñ : = i[0]á 5:7ñ

register address

dá 0:15ñ : = i[1:2]á 0:7ñ

16 bit address

4.4 Effective Address Calculation Process. This process is declared using the assignment command (:=) and is evoked each time an instruction makes reference to a variable that is taken to be an effective address or an operand. In the book operands have two forms. Most of the time they are expressed as memories and address expressions using the effect address calculation process; otherwise the operands are defined by a process.

4.5 Data-type Format and Special Data-Operation Definitions. The component parts of the data-types are named, and their element ranges are first defined, so that the data-operation definitions can use them. For example, a precise definition of an ISP would include the data-type formats (for example, floating-point), follow d by a definition of each data operation (for example, +, -, x, /). Normally, we do not give enough information about the data-type and its appropriate operation implementation in our description of machines, since the information for these descriptions is obtained from the programming manuals. If we were actually to use the ISP descriptions, as an interpreter using a compiled or interpreted language, then only a few well-defined primitives would exist in the language and all other operations would have to be defined in terms of these primitives for each ISP. ISP 2 and ISP 3 describe how the various data-types and operations are declared.

4.6 Instruction Interpretation Process. In the definition of processors, the only part that is executed is the instruction interpreter. All the other parts are memory data declarations and processes to be carried out as an indirect consequence of the interpretation process. The format for most interpreters is the familiar fetch-the-instruction then execute-the-instruction pair of states, and consists of only one ISP statement.

EXAMPLE

Run ® (instruction ¬ M[PC]; PC ¬ PC + 1; next fetch (PC/program counter)
Instruction_ execution) execute

In more complex processors the conditions for trapping and interrupting must be described. Also, in the interpretation process it is often more descriptive to carry out part of effective address calculation prior to Instruction_ execution. See below.

The IBM 1401 interpreter (Chap. 18) requires a separate process to fetch the operands addresses prior to execution in a variable-length instruction. The fetch is based on the specific instruction to be executed next.

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