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260 Part 3 The instruction-set processor level: variations in the processor

Section 5 Processors with stack memories (zero addresses per instruction)

Fig. 5. Burroughs B 6500, B 7500 peripheral K-T PMS diagrams.

to be both overdesigned (or overly general) and there are too few of them. The limit of only 16(T + Ms) components is small, especially considering that the KDF9 is to be time-shared from several consoles.

The ISP of the examples
The comparison of Pc.stack, Pc.1address, and Pc.general_ registers (page 64) makes the assumption that an unlimited

Fig. 6. English Electric KDF9 PMS diagram.

hardware stack resides in Pc. The B 5500 has a local M.stack in Pc of 4 words. The size and number of stacks, and their use by software, are most important. The IPL-VI machine has any number of stacks since the front of each list is a stack. The KDF9 (Fig. 6) has two independent stacks: one for arithmetic expression evaluation and one for holding subroutine return addresses. The DEC 338 P.display (Chap. 25) uses a stack for storing subroutine return addresses.

Unfortunately, we have not been able to include a discussion of the "cactus stack" of the B 6500, which is a data structure more like a list [Hauck and Dent, 1968]. The Hauck and Dent paper describes both the relationship to a Pc.stack and its relevance to program mapping and memory management for multiprogramming.

The C('D825) parameters are given in Fig. 7. The D825 ISP differs from other Pc.stack computers in that the data, d, for operations can be in either of two places, the stack or Mp. Consider the unary or binary operations:

Fig. 7. Burroughs D825 PMS diagram.

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