258 Part 3 The instruction-set processor level: variations in the processor
Section 5÷ Processors with stack memories (zero addresses per instruction)
Fig. 1. Burroughs B 5000 PMS diagram.
and delete, respectively). Thus a list is like a nested set of overlapping stacks. EULER (Chap. 32) uses a stack to store temporary data and subroutine calls both when compiling and when interpreting the compiled program. However, the language-based machines can still be studied profitably with the stack in mind.
The following comments will be directed to the P.stack computers manufactured by both English Electric and Burroughs. There are three basic P.stack computer families: B 5000 ® B 5500® B 6500/B 7500; D825 ® D830 ® B 8500; and KDF9. Each root member was made available at about the same time by Burroughs (Pasadena, Calif.), Burroughs (Paoli, Pa.), and English Electric. The IBM Corporation later responded with a proposed Pc.stack, but the machine never entered the production phase.
The Pc.stack is a major alternative to the main line organization of 1 address per instruction (augmented with index registers or general registers). It tries to capitalize on the hierarchical character of computation to avoid having to give memory shuffling instructions explicitly. In Chap. 3, page 64, we gave a comparison of a trivial computation using a stack and a general-register organization, in order to make clear the case
Fig. 2. B 6500, B 7500 PMS diagram.