504 THE PDP-10 FAMILY
The asynchronous bus avoided the problem of distributing a single high-speed clock and al lowed interleaved memory operation.
Modularity was also introduced to clarify organizational boundaries within the company and to make possible low cost, special purpose production and engineering testers for the memory and I/O equipment. We believe that the concept of well defined modules was relatively unique, especially for memory, and was the basis for the formation of third party add- on memory vendors. MIT and Stanford University purchased memories from Fabritek and AMPEX, respectively, in the mid-1960s to start this trend. (Note that this design style differed from the IBM System/360 design with its relatively bounded configurations and integrated memory. Add-on memory did not appear until the early 70s for the IBM machines because, we believe, of the difficulty of the interface definition.)
The KI10 memory system was improved by assigning signals to request multiple, overlapped memory accesses and to increase the address size from 18 bits to 24 bits. The additional physical memory addresses are mapped into a program's 18-bit addresses via the core-held page table.
The KL10 processor-memory organization was a significant departure from the KI10 as previously discussed. The KL20 eliminated the original Memory Bus to provide an integrated system. It should be noted that this evolution was based on the drastic size reduction (a factor of about 300) from a single cabinet (6 ft X 19 in X 25 in or about 34,000 in3) for 16 Kwords to a single logic module for 16 Kwords (15 in)( 8 in X 1 in or about 120 in3).
PM S Structures for Computer-Computer Intercommunication
Throughout the evolution, a number of schemes have been used to interconnect with other (usually smaller) computers. The schemes are given in Table 5. Note that the first four