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The decision not to use the IBM-type channel structure was based on high overhead (cost) in both programming and hardware. Because I/O record transmission usually caused a central processor action, we felt the processor might as well transfer the data while it had access to it. This merely required a good interrupt and context switching mechanism, not another specialized processing entity. However, when an inordinately high fraction of the processor's time went to I/O processing, a second, fully general processor was added - not a processor that was fundamentally only capable of data transmission.

The PDP-6 interrupt scheme was based on our previous experience with a 16-level and 256-level interrupt mechanism for PDP-1. The PDP-1 scheme was an extension of the Lincoln Laboratory TX-2 [Clark, 1957]. The PDP-6 had a 7-channel interrupt system, and each device on the I/O Bus could be programmed to a particular level. Hence, a programmer could change the priority of a particular device that caused interrupts on the basis of need or urgency. The PDP-6 also had an I/O instruction ("block input" or "block output") to transfer a single data item between a block (vector) in primary memory and an I/O device. Thus, as each word was assembled by a controller, an interrupt occurred; the block transfer was executed for one word, taking only three memory references (to the instruction, to increment the address pointer and block counter, and to transfer data). Most of the hardware to control the count and address pointer was already part of the processor logic.

In applications requiring higher data transmission (e.g., swapping drums, disks, TV cameras), a controller with a data buffer (erroneously called an I/O Processor) and link to memory was provided. This controller required only a single memory reference per data transfer with the address pointer and block counter in hardware. In the KA10, the name was changed to Channel, and parameters for transferring contiguous records into various parts of memory were part of the channel's control. The device control was via the I/O Bus; hence, we ended up with a structure for high speed device control not unlike the IBM channels we originally wanted to avoid.

Competitive pressure from the Xerox Sigma series caused a change in the way interrupts were handled beginning with the KI10. Although the Xerox scheme had many priority levels, its main utility was derived from rapid dispatch to attend to a particular interrupt signal. We kept compatibility with the 7-channel interrupt by using a spare wire in the bus and adding the ability to directly dispatch to a particular program when a request occurred. At the interruption, the processor sent a signal to requesting devices and the highest priority device responded with a 33-bit command (3-bit function, 18-bit address, 12-bit data). The functions were: (1) execute the instruction found at addressed location, (2) transfer a word to/from addressed location, (3) trap to addressed location, and (4) add data to addressed location. Little use was made of these functions (especially number 4), since only a small number of devices were typically connected to a large system, thus relaxing the requirement of rapid dispatch. Summarily, the problem of competition was resolved when Xerox left the competitive scene. In systems that had a large number of devices, a front-end I/O processing minicomputer was more cost-effective than central processor controlled I/O.

Memory System

Because it was unclear how memory technology would affect memory speed, a completely asynchronous, interlocked Memory Bus was designed. Thus, the 16 fast general registers, the initial 5-microsecond memory, and the next generation 2 microsecond memory could all operate on a single system. (Most memories are now less than 1-microsecond cycle time.)

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