previous | contents | next

502 THE PDP-10 FAMILY

Figure 6. PMS diagram for KL10 processor-based system.

Mwords/second yielding a maximum 12.8 Mwords/second transfer rate for all channels. However, contemporary disks need about 250 Kwords/second so that all eight channels only require 2.0 Mwords/second of the 4 Mword/second memory bandwidth of four modules. Individual disks and tapes can be connected to a second port for increased concurrency. For larger memory configurations, a memory bandwidth of 16 Mwords/second is not uncommon. A 2 Kword processor cache provides roughly a 90 percent hit rate and reduces memory bandwidth demand by nearly a factor of ten.

The cost-reduced KL20 evolved by integrating the Massbus controllers and PDP-l1 interfaces onto a single high-speed, synchronous bus. The model 2040 and 2050 computers are based on the KL10 processor and integrate 256 Kwords of memory in a single cabinet with the processor (thereby eliminating the external Memory Bus). The I/O Bus is also eliminated, and all I/O transfers are either via the Massbuses or the PDP-l1 I/0 computers. (It must be noted that the 2040 structure is possible only because of the drastic increase in logic and memory density!)

I/O System

Relatively, low speed I/O (200 Kwords/ second) in the PDP-6 was designed to be under central processor programmed control rather than via specialized I/O processors (IBM System 360/370 Channels). This method had proven effective in our minicomputers and was extended to handle higher data rates with lower overhead than specialized I/O processors.

previous | contents | next