496 THE PDP-10 FAMILY
Table 4. Comparison of Stack and General Register Architectures
keep track of) their use. In fact, Lunde  has shown that eight working registers would be sufficient to support the higher level language usage. Multiple register sets were introduced in the KI10 to reduce context-switching time.
Instruction-Set Encoding and Layout
The ease-of-implementation goal forced an instruction set design style that later turned out to be easy to fabricate with the KL10 microprogram implementation. This also simplified the fabrication of compilers. In fact, of the 222 instructions useful for FORTRAN data-types, the earliest compiler used 180 of them and the current compiler uses 212. We used three principles, we now understand, for the ISP design:
1. Orthogonality. An address (with index and indirect control fields) is always computed in the same way, independent of the data-type it references. Indirect addressing occurs as long as the instruction addressed has an indirect bit.
2. Completeness and symmetry. Where possible, each arithmetic data-type should have a complete and identical set of operations.
3. Mapping among data-types. Instructions should exist to convert among all data-types. Several data-types were incomplete (characters, half-words), and these should be converted to data-types with a complete operator set.
The instruction is mapped into the 36-bit word as follows:
The entire instruction set fits easily within a single figure (Figure 2). The boldface letters denote instruction mnemonics. The data-types and operations are generally deducible by the instruction names: operator names (e.g., ADD) for word (or integer); D double integers; H half-world; BL vector; 16-operator names (e.g., AND) for Boolean vectors, Test-Boolean (bits); J jump/skip for program control; F floating; DF double floating. The I/O and interrupt instructions are described in the PMS section.