494 THE PDP-10 FAMILY
3. Arbitrary length field access (load/store only).
5. Programs (loops, branching, and sub programs).
6. Ordinary integers.
7. The control of I/O.
A significant number of control instructions were included to test addresses and other data-types. These tests controlled flow by either a jump or skip of the next instruction (which is usually a jump). Loop control was a most important design consideration.
Table 3 gives the data-types and instructions present in the various implementations. The KA10 and PDP-6 processor instruction sets were essentially the same, but differed in the implementation. The PDP-6 had 365 instructions. A double-precision negate instruction in the KA10 improved the subroutine performance for double-precision reals. The instruction, "find first one in a bit vector," was also added to assist operating system resource allocation and to help in a specific application sale (that did not materialize). Finally, double-precision real-arithmetic instructions were added to the KI10 using the original PDP-6 programmed scheme. A few minor incompatibilities were introduced in the KI to improve performance.
With the decision to offer COBOL in 1970, better character and decimal string processing support was required from the instruction set. The initial COBOL performance was poor for character and decimal arithmetic because each operation required: (1) software character by character conversion to an integer, (2) the operation (in binary or double-precision binary), and (3) software reconversion to a character or a decimal number. The KL1O provided much higher performance for COBOL by having the basic instructions for comparing character and decimal strings - where a character can be a variable size. For arithmetic operations, instructions were added to convert between string and double-precision binary. The actual operations are still carried out in binary. For add and subtract, the time is slightly longer than a pure string-based instruction, but for multiplying and dividing, the conversion approach is faster.
Stack Versus General Registers Organization
A stack machine was considered, based on the B5000 and George Interpreter (which later became the English Electric KDF9). A stack with index register machine was proposed for executing the operating system, LISP, and FORTRAN; it was rejected on the basis of high cost and fear of poor performance. The compromise we made was to provide a number of instructions to operate on a stack, yet to use the general registers as stack pointers.
An interesting result of our experience was that one of us (Bell) discovered a more general structure whereby either a stack or general register machine could be implemented by extending addressing modes and using the general registers for stack pointers. This scheme was the basis of the PDP-l1 ISP (Chapter 9).
We currently believe that stack and general register structures are quite similar and tend to offer a tradeoff between control (either in a program or in the interpretation of the ISP) and performance. Compilers for general register machines often allocate registers as though they were a stack. Table 4 compares the stack and general register approaches.
A general register architecture was selected with the registers in the memory address space. The general registers (multiple accumulators) should permit' a wide (general) range of use. Both 8 and 16 were considered. By the time the uses were enumerated, especially to store inner loops, we believed 16 were needed. They could be used as: base and index, set of Booleans (flags), ordinary accumulator and multiplier-quotient (from 7090), subroutine linkage, fast