USING LSI PROCESSOR BIT-SLICES TO BUILD A PDP-11 461

lists, stuff lists, error reports (wire-ANDing violations, etc.), and loading analyses, which all proved extremely helpful.

The logic simulator used was Simulation of Asynchronous Gate Elements (SAGE), which is a 4-state (0, 1, high impedance for tri-state buses, and undefined for initialization and uncertainty in delay parameters) gate-level simulator. It reads the data base directly from the output of the SUDS for utmost convenience, since it allowed a turnaround time in the order of five minutes for print set corrections. SAGE has models in its libraries for the TTL and Schottky families, and special routines were written by us to emulate the 3000 microcomputer set. This allowed improvements in the efficiency of the simulation execution. Macro facilities are also available for quickly defining MSI circuits from more basic logic gates. The results of the simulations are in the form of register and signal reports and timing/trace diagrams.

About 95 percent of the original design errors were eliminated through the use of the simulation program. Naturally, not all combinations and sequences of instructions can be simulated, but a standard PDP-l1 diagnostic program was run in addition to a number of other programs. A total of about 100 milliseconds of CMU-l1 compute time was simulated before debugging on the actual hardware began.

The limitation here was that the SAGE simulation of the CMU-11 required about 10⁶ seconds of CPU time on a PDP-10 to simulate 1 second of CMU- 11 execution. We simply could not afford to consume more than about 30 hours of CPU time for this project.

Whatever amount of time is spent on simulation, the simulations cannot be exhaustive and the final set of errors must be tracked down with more extensive tests on the real machine. We discovered eight to ten errors in the actual CMU- 11. However, when an error was found in the physical machine, the simulations were again run to help track down the bug through the use of timing traces and other results. The correction was then entered into the machine print set and the simulator was rerun before implementing the change on the processor wire-wrap board or in the microprogram.

An example of the worth of the computer-aided design system came to light when a major implementation change was made; several ROMs were incorporated into the design to replace a discontinued programmable logic array (PLA). Our design aids were essential in effecting this change within four man-days. In order to recover so quickly from such a massive wiring change, an engineering change order (ECO) wrap/unwrap program was run to compare the old and new wire-lists produced by the drawing package. Thus, at all times during development, the processor reflected the exact connectivity of the print set.

Several of the errors discovered on the real machine were timing errors that were not revealed in the simulation debugging. These errors were not detected because the simulation models did not consider the effects of loading on the propagation delays and only maximum delays in all gates were used as an approximation to worst case conditions. In fact, if time had permitted, minimum and "typical" (Gaussian-distributed) parameters should also have been tested. However, we again face a fundamental problem with simulation in that the computation time becomes excessive as different sets of delays are simulated to find worst-case conditions.

The CMU-l1 project was initiated as an experiment in constructing general purpose (mini) processors with LSI bit-slice components. Table 8 is a summary of the results. As the table