THE DESCRIPTION AND USE OF REGISTER TRANSFER MODULES 447
errors. The computer was designed for an actual application that had about 300 constants, 600 control steps, and about 16 variables. (An alternative approach would have been to hard- wire the 600 control steps directly, thereby operating faster, but being more expensive and less flexible.) The computer has only 24 evoke and 16 branch controls. (By way of comparison. RTM interpreters to emulate the PDP-8 and the Data General NOVA computers require about 90 evoke and branch control modules, 2 DM.gpa's, and core memory.) Since the price ratio of a single hardwired control to a single read-only memory control word is approximately 10:1, and since the overhead price of a 1000-word read-only memory is about 100 controls, it was cheaper in the above application to use RTMs to first build an interpreter, commonly called a stored program digital computer, and then let the computer program execute the control steps.
The data part of the machine is shown in the upper right of Figure 4. Three DM-type RTMs hold the processor state and temporary registers. The processor state, that part of memory accessible and controlled by the program, includes: A, the accumulator; P, the program counter; and L, a register used to hold subroutine return addresses (links). The temporary registers needed in the interpretation of the instructions are: i, instruction holding register; and B, used for binary operations on A (e.g., Add, And). Also connected to the RIM bus are the read-only and read-write memories and the Teletype, as well as a special input/output register interface to the remainder of the system.
The method of defining the interpreter can be seen from the RTM diagram (Figure 4). The control part consists of three subparts: the Start and Continue keys that are used to initialize the processor to start at location 0 and to restart the processor, the instruction fetch, and the instruction execution. The instruction fetch consists of picking up the instruction from the memory word addressed by the program counter P and incrementing P to point to the next instruction. The instruction is placed in the i register, which has been specially wired to allow decoding of the three most significant bits. Individual bits of can be tested for the Operate (OPR) instruction, and the address field i< 10:0> can be read.
After the instruction is fetched and placed in i, Ke(MA¬ i< 10:0>) is evoked to address data referenced by the instruction. Immediately following this evoke operation, an eight-way K.branch allows control to move to the one path corresponding to the operation code of the instruction being interpreted; that is, the instruction is decoded, and control is transferred to execute it. After the execution of the appropriate instruction, control returns to fetch the next instruction. For example, executing the Add (two's complement add) instruction consists of loading the data from memory into the temporary register B (i.e., B ¬ MB) and then adding B to the accumulator A (i.e., A¬ A+B).
For the Operate instruction, which does not reference memory, each bit of the address part of the instruction specifies an operation to be carried out on the accumulator ("test for - or 0," "clear, "complement," "add one," "shift right or left," or "return from the subroutine"). Each bit is tested in sequence, and if a one, the corresponding operation is carried out. If the instruction code with OP=6 is given, the computer halts; pressing Continue restarts it.
The instruction set is shown to be straightforward and simple. Subroutine return addresses are stored in a link register L. Thus to call subroutines at a depth of more than one level requires the called subroutine to save the link register in a temporary location. But there is no way of storing this register; thus it is difficult to call a subroutine and pass parameter information (e.g., the location of tables). Since the computer requires a few minor changes to allow nested subroutines and parameter passing, the reader is invited to make the appropriate incremental changes.