IMPACT OF IMPLEMENTATION DESIGN TRADEOFFS ON PERFORMANCE: THE PDP-11, A CASE STUDY 329

Figure 2. Archetypal medium-range PDP-11 data paths.

and two's complementation, and logical ANDing and ORing.

The inputs to the ALU are the A leg and the B leg. The A leg is normally fed from a multiplexer (A leg MUX) which may select from an operand supplied to it from the Scratchpad Memory (SPM) and possibly from a small set of constants and/or the Processor Status register (PS). The B leg also is typically fed from its own MUX (B leg MUX), its selections being from the B Register and certain constants. In addition, the B leg MUX may be configured so that byte selection, sign extension, and other functions may be performed on the operand which it supplies to the ALU.

Following the ALU is a multiplexer (the A MUX) typically used to select between the output of the ALU, the data lines of the Unibus, and certain constants. The output of the A MUX provides the only feedback path in all mid-range PDP-1 1 implementations except the 11/60 and acts as an input to all major processor registers.

The internal registers lie at the beginning of the data paths. The Instruction Register (IR) contains the current instruction. The Bus Address register (BA) holds the address placed on the Unibus by the processor. The Program Status register (PS) contains the processor priority, memory management unit modes, condition code flags, and instruction trace trap enable bit. The Scratchpad Memory (SPM) is an array of 16 individually addressable registers which include the general registers (R0-R7) plus a number of internal registers not accessible to the programmer. The B Register (B Reg) is used to hold the B leg operand supplied to the ALU.

The variations from this archetype are minor as discussed in the section entitled "Characterization of Individual Implementations." Variations encountered include routings for Bus Address and Processor Status register, the point of generation for certain constants, the positioning of the byte swapper, sign extender, and rotate/shift logic, and the use of certain auxiliary registers present in some designs and not others. In general, these variations are all peripheral to the major elements and interconnections of the data paths.

Control Unit. The control unit for all PDP-11 processors (with the exception of the PDP-11/20) is microprogrammed [Wilkes and Stringer, 1953]. The considerations leading to the use of this style of control implementation in the PDP-11 are discussed in [O'Loughlin, 1975]. The major advantage of micro- programming is flexibility in the derivation of control signals to gate register transfers, synchronization with Unibus logic, control of microcycle timing, and evocation of changes in control flow. The way in which a micro programmed control unit accomplishes all of these actions impacts performance.

Figure 3 represents the archetypal PDP- 11 microprogrammed control unit. The contents of the Microaddress Register determine the cur rent control unit state and are used to access the next microinstruction word from the control store. Pulses from the clock generator strobe the Microword and Microaddress Registers loading them with the next microword and next microaddress respectively. Repeated clock pulses thus cause the control unit to sequence through a series of states. The period spent by the control unit in one state is called a micro cycle (or simply cycle when this does not lead to