316 THE PDP-11 FAMILY

Figure 1. Minicomputer family evolution. Advances in technology translate into two design styles: constant cost/increasing functionality and constant functionality/decreasing cost. The PD P-11/60 represents former design style. Functionality added to PDP-11/40 is depicted by shaded area. Tradeoffs discussed occur within this area.

Figure 2. Internal structure. Cache placement between Unibus and CPU permits faster execution and allows use of standard memories. However. DMA monitoring mechanism is needed for traffic on path CBA. Module count is six for CPU and cache, one for writable control store, one for microdiagnostics unit, and four for floating-point processor. This processor operates in parallel with CPU execution of nonfloating-point instructions; instruction times are 1.02 m s for double-precision add and 1.53 m s for single-precision multiply. Writable control store uses 1024 control words that are reloadable and that control 170 ns inner machine. Machine is design optimized for user environment characterized by real-time operating system and FORTRAN.

Lower cost members trace the decreasing cost/constant functionality curve. (This is the 11/20, 11/05, and LSI-11 or 11/03 line.) The horizontal line in Figure 1 connects the constant cost/increasing functionality designs. (Not shown are "growth-path" members that provide greater performance at slightly increased costs; 11/45, 11/55, and 11/70 machines trace an upward growth-path curve.) Shaded area in the figure represents the added functionality possible through technology advances. Mid-range minicomputers attempt to optimize price/functionality and, hence, offer an excellent vantage point for discussing design tradeoffs made under the constant-cost design style.

In addition to the capabilities provided by technological advances, a mature family architecture and user base allows the minicomputer designer to include those capabilities that were not considered feasible in the original architecture. These features may not have been included because they were too costly to implement, not sufficiently general purpose to justify their inclusion, or not perceived as being essential to users. Reliability, maintainability, the integral floating-point unit, and the writable control store (WCS) option represent such capabilities.

Internal structure of the 11/60 (Figure 2) incorporates a 2048-byte cache, memory management unit (for virtual-to-physical address translation), and an integral floating-point unit as standard components. The unit can perform a register-to-register add instruction in an average time of 530 ns; internal cycle time is 170 ns. Available as options are a floating-point processor, which implements at higher speed the same 46 instructions as the integral unit, a writable control store, and a microdiagnostic unit.

Improvements in memory technology have been the principal forces in minicomputer de-