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BUSES, THE SKELETON OF COMPUTER STRUCTURES 271

DATA BUS READ SEQUENCE

1. A read command is loaded into the Control register of the drive. If the command is valid, the drive enables its data bus receivers and drivers and asserts OCC.

2. Not more than 100 microseconds after step 1, the controller asserts RUN.

3. After a cable delay, the drive receives the RUN assertion. Disk drives now begin searching for the desired sector. Tape drives begin tape motion.

4. When the drive has read the first data word, it generates parity for the word; the data and OPA are gated onto the data lines and SCLK is asserted.

5 After a cable delay, the controller receives the SCLK assertion.

6. The drive negates SCLK no less than T nanoseconds after asserting it. where T is either 225 nanoseconds or 30 percent of the nominal burst data period of the drive, whichever is greater. The Data lines should be maintained valid for no less than one half of the SCLK interval after SCLK is negated.

7. After a cable delay, the controller receives the SCLK negation. The controller strobes the D lines and DPA and checks parity.

8. If there is more data to be read in this block, then not less than T nanoseconds after step 6, the drive gates out the next data word onto the D lines, generates DPA, and asserts SCLK. Steps 5, 6, and 7 then follow.

9. After the negation of SCLK (step 6) on the last word of data in the block, the drive asserts EBL.

10. After a cable delay, the controller receives the EBL assertion. At this time, the controller must decide whether or not to have the drive read the next block of data without disconnecting from the data bus (the controller may already have negated the RUN line).

11. If the controller decides not to read the next block, it negates the RUN line not later than 500 nanoseconds after step 10.

12. After a cable delay, the drive receives the RUN negation (the RUN line may already have been negated).

13. Not less than 1500 nanoseconds after step 8, the drive negates EBL At this time the drive strobes the RUN line. If RUN has been negated, the drive disconnects from the data bus (the DRY bit should be set and OCC negated at this time).

14. After a cable delay, the controller receives the EBL negation (the controller may now generate an end-of-transfer interrupt and start another data transfer).

Figure 1. The Massbus Data Read operation as described in the Massbus specification.

 

specification is a list of the design problems that came up during the engineering of connections to it and the details of how they were resolved. This was done for the Massbus, in a section of the specification called "Design Notes."

FUNCTIONS OF BUSES IN COMPUTER SYSTEMS: A FIVE-FUNCTION MODEL

The functional building blocks of computers are central processing units, primary memory, input/output controllers, and peripheral units. Peripherals tend to be classed as either secondary memory or transducers (usually terminals).

Figure 4 shows these components in a traditional single-processor minicomputer system. Five different paths are shown interconnecting these components. These paths do not represent

Figure 2. The Data Read flowchart in the Massbus specification.


actual buses. Instead, we have considered each pair of components in the system and asked whether they need to communicate with each other. If so, a pathway between the pair has been inserted. This leads to a model which has more interconnection pathways than a typical computer has.

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