156 BEGINNING OF THE MINICOMPUTER

Figure 27. PDP-9 front and back logic layout.

Figure 28. PDP-9 system block diagram.

Except for the 300 wire field change on the first ten processor backplanes, the PDP-9 enjoyed a good reputation for performance and up time. It was followed by a less costly version, the PDP-9/L. The cost reduction was accomplished by using a new (and somewhat cumbersome) power supply design and by offering a 4- Kword minimal system with lower cost paper tape equipment. The 4-Kword memory planes were borrowed from the PDP-8 line and adapted to provide half the memory in half the space. To provide lower cost paper tape capability, the PDP-9/L used a teleprinter equipped with paper tape reader and punch instead of a separate, heavy-duty paper tape reader and punch. The product life of the PDP-9/L was relatively short; it was soon made obsolete by the PDP-15.

Unlike its predecessors, the PDP-15 was designed to provide a range of systems with both hardware and software. While early 18-bit machines had evolved to include several configurations, the notion of a planned range for PDP-15 systems was explicit from the start. As it turned out, the PDP-15 evolved too, and over a considerably larger range than was anticipated. Table 2 shows the range of systems that eventually developed; of these, only the models up through 15/40 were in the original plan.

As in the past, the goal for the new machine was to provide better performance/cost than the predecessor. The PDP-7 to PDP-9 transition had provided a performance improvement, but not a big cost improvement. The new semiconductor technology, transistor-transistor logic (TTL) available in dual inline packages, could provide the cost improvement required. The 7400 and 74H00 series of TTL integrated circuits permitted clock speeds of 10 to 20 MHz and lower costs and higher packing densities than did the discrete circuits used in the PDP-9. Not only did the higher packing densities lower the packaging costs, but they also permitted the