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that direction. The project was called the "VHF Logic" project because operation at 30 MHz or better (the bottom end of the very high frequency (VHF) radio band) was the goal.

The complex 30-MHz flip-flops were packaged one to a module (Figure 15), with the result that a great many interconnections were needed to implement logic functions. In systems designed for 30-MHz operation, the use of leads longer than a few centimeters was expected to require special care; hence, it was thought essential for ease of use that a satisfactory transmission line hookup medium be available. A new solid wall coaxial cable had just been introduced, the 50-ohm impedance version of which was chosen to hook up the VHF modules. It appeared to have a strong enough center conductor for practical hookup between modules without being too bulky for easy hand- bending.

Due to the low impedance needed for the coaxial cable connections, substantial driving current was necessary to achieve adequately high signal voltages, and considerable power had to be dissipated. The ability to drive a load at any point along the transmission line was deemed necessary for practical hookup, and 3- volt swings had to be available to insure compatibility with existing modules. These needs were met by choosing a 60-milliampere output current, producing a 1.5-volt swing on a double-terminated 50-ohm line and a 3-volt swing with a 50-ohm load when interfacing to existing slower logic. These voltage and current levels required the addition of heat sinks to the output transistors. This was accomplished by installing spring clips that fastened the-cases of the transistors directly to the connector pins, exploiting the connectors as heat sinks and at the same time providing a minimum inductance connection from the transistor collector (common to the case) out of the module.

The VHF modules contained a novel delay line implementation which has reappeared in recent days in the emitter-coupled logic boards used in the latest PDP-l0 processor (KL10). Flip-flop output delay was provided by a 10- nanosecond stripline etched onto the printed circuit board. A meander pattern was selected with a degree of local coupling between the loops to achieve a 7 to 1 delay-to-risetime ratio. Both the delayed and undelayed ends of this 50- ohm stripline were made available at the module pins. The undelayed outputs switched simultaneously with the flip-flop outputs, allowing a subsequent gate to subtract a delayed flip-flop output from the undelayed complement output side of the flip-flop and produce a 10-nanosecond pulse when the flip-flop changed state.

The performance of the VHF modules was rated at 30 MHz, which was the limit of the module testers used on the production floor. Bench testing demonstrated 40-MHz capability with the promise of 50-MHz performance if adequate testing apparatus could be found. Rise- times were better than 1 nanosecond.

Modules delivered to customers were used to build satisfactory high performance systems, but the need for such high performance was not widespread. In addition, the product development cycle was, by the standards of the time, quite long (two years) and enthusiasm for the VHF modules among DEC engineers waned, further slowing product momentum. Despite their failure as a product, with only eight modules in the series, the VHF modules eventually made a contribution to computer progress. To produce timesharing systems, the PDP-6 needed a way of comparing relocated addresses at very high speed. A high speed register comparator was quickly designed using current mode logic similar to that in the VHF modules.

As a series of general purpose products for engineers to use, the VHF modules were too costly and their wiring too inconvenient. Further developments in general purpose logic modules were to lie in the opposite direction: toward cheaper, more compact, easier to use, and slower units.

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