becomes Low, then another data sender was also evoked and supplied the DR signal.
Care should be exercised when. a register's content is checked .by probing. For example, the latches of an M(transfer) are active as long as the evoke which enables them to read is active. Thus probing an M(transfer) while its read input is active could cause erroneous data to be entered.
Another way to detect incorrectly read data is to-remove the receiver at each step in the flowchart and see if a DA signal is generated. If a DA signal appears, then a multiple read from the Bus was incorrectly performed at that flowchart step.
It should be noted that unless Boolean branch variables are brought out to light they are unobservable. An erroneous data transfer (appearing on the Bus) may be due to the system taking an incorrect branch. The branches can be forced to a one state by leaving their inputs floating By removing the inputs to a Boolean branch of the flowchart, the system will take a path that is uniquely determined (assuming the K(branch) is not faulty). This will help detect wiring errors associated with the K(branch) modules. Observation of the Boolean inputs to the K(branch) modules at each branch situation of the flowchart will also help locate wiring errors.
Sometimes an RTM system will operate in manual-single step mode but will not operate properly at full speed. An oscilloscope can observe the K(evoke) following a K(branch). If the K(evoke) is supposed to be activated and is not, isolation is achieved by observing where the system first deviates from the flowchart. Checking earlier branch points is a good isolation procedure. If in doubt as to whether a timing problem actually exists, operate the system in manual-single step mode at different pulsing rates to see' if the system operation is intermittently incorrect.
In order to facilitate debugging, the design should include testing facilities and a plan for testing. For example, software programs are debugged by dividing the program functions into several small subroutines and debugging the subroutines individually. By using K(subroutine) modules an RTM system can be divided into small, easy to test blocks. Also, (daisy) chaining wires is often suggested to distribute a signal to many pins. However, daisy chaining makes it difficult to trace wiring. For example, tracing a wire to a pin which has three wires attached to it means the traced wire could have one of two origins. If the traced wire does not have an active signal on it, detection of the relevant source wire is extremely difficult.
After the modules have been manufactured they have to be tested to insure that they will meet specification. Normally this is done by the manufacturer, but in a laboratory environment it is possible to introduce defects. It will be assumed that an RTM system has been built that exercises all of the functions of the module to be tested. Thus a newly manufactured or an aged and suspected faulty module would be plugged into the test system. Any detected fault in the module under test would cause the test system to indicate an error. If the test system completed its designed operation, then the module under test would be accepted as fault free. Some of the modules, such as K(branch) and K(evoke) are easy to test on a functional basis, while others, such as a DMgpa, are quite complex. The simpler modules can be functionally tested by observing the module outputs for all possible module inputs. Since the number of inputs and
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