deviation would have created very high setup costs. Also, since most users of IC's have previously made the same decision, the manufacturing cost of' TTL is lower. In fact, reasons for using, say ECL, such as higher speed and higher noise immunity, were not of sufficient importance to overcome the extra manufacturing, development, and setup costs.
Another constraint related to current MSI technology is word length. Integrated Circuit registers and data operations are commonly available in packages of four or eight bits. Furthermore, problems in the computer area usually dictate the use of word lengths of 8, 12, or 16 bits. Thus there was no conflict in choosing these word lengths for RTM's. If a need for word lengths of larger than 16 bits materializes, the word length can be extended by producing another set of modules.
SET OF MODULES
In view of the constraints discussed above and shown in Figure 1, a final set of engineering decisions was made regarding the modules. Some of the more important ones are listed in the table in Figure 2.
This section deals with the switching circuit level design of RTM's. Much of this design is straightforward and conventional and will not be covered in any detail. Instead, those aspects of the design that give RTM's a unique, modular behavior will be presented. The intention herein is to assist the potential module designer, and also to provide enough detail so that one could extend the RTM concept by interfacing various components into the RTM framework.
CONTROL SIGNAL TIMING DIAGRAMS
The most interesting and most important characteristic of RTM's is the method used to pass control among the K modules and between the K portion of a system and its DM part. That is, how do K modules activate one another, and how do they evoke operations in the DM part of the system? These questions can be answered by first looking at a control signal timing diagram for two sequentially connected K(evokes). Two such modules are shown in Figure 3.(1) They both evoke simple register transfers on the RTM Bus. The control signal sequence for their operation is shown in the, timing diagram in Figure 4. The diagram uses arrows to show the cause and effect relationship between events. Notice that each logic level change is an event, and signals are at the logical Low level for assertion, i.e., negative logic is used. The interpretation of the sequence is as follows:
1. The activate input to Ke2 is asserted by Kel, thus asserting the evoke- operation inputs to the appropriate DM modules to evoke the desired operation.
2. When the data from the source DM module (i.e., the source of C) is ready, that module asserts the DATA READY\DR signal on the Bus.
3. When the receiving DM module (i.e., the module containing the B register) senses the DR signal, it accepts the data on the Bus and asserts the DATA ACCEPTED\DA signal on the Bus.
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1. Here the RTM boxed notation is superimposed on DEC's PDP-16 notation. Since we are discussing DEC's implementation of the modules, we shall use mostly the PDP-16 notation in this chapter.
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