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a DMgpa is used for updating the clock A clock count flag is set each 10 microseconds by the master clock, and the control part senses the state of the flag and then increments C[1:3] by 1.

The computer transmits a control word to the clock which signifies which of the two functions are to be performed. For resetting the clock, a non-zero word is transmitted to the clock, signifying that the next three values will be transmitted to reset C[1:3]. When this occurs, the sequence to reset the clock is invoked, and clock counting is stopped until all three words are placed in the clock registers.

A zero word is transmitted from the computer to the clock-calendar signifying that the three values of C are to be transmitted back. Unlike the case of resetting C, it is necessary for the clock to continue while the read-in process occurs. Also, the clock must not change during this process, since a carry might be generated and cause subsequent words to change. Note that adding a value to C is just a triple word addition by 1. While transmitting C[1:3] to the computer, counting is carried out in an intermediate register, and after C[ 1:3] is transmitted, the intermediate counts are added back to C to update it. (Alternatively, the clock might have transmitted C[3] to the computer on command and then continued to count C[3] while only keeping an overflow from C[3] for eventual update of C[1:2].)


1. Design the mixed-base system, which provides time units that can be read directly by humans.


KEYWORDS: General register, minicomputer, ISP

Cgr, a stored program minicomputer with multiple general purpose registers (i.e., Accumulators) is presented using ISP to give the reader an idea of another type of computer.(4) The implementation is similar in size to the DEC PDP-8 implementation.


The implementation is to be based on the Instruction-set definition in Figure Cgr-1, given in ISP.

The processor state memory is five words + 2 bits: P<0:15>, A[0:3]<0:15>, Run and Carry-flag. The physical program primary memory is 2^15 words, declared as Mp[0:32767v10]<0:15>. Two 17-bit intermediate result registers, shifter and result, are needed in the description to correspond to outputs of Data operations in the actual machine.

Two instruction formats are given: the operate instruction that specifies the operations to be carried out on the four Accumulator\A registers; and instructions which address operands for loading and storing the A registers and for modifying memory (i.e., incrementing and decrementing by 1). The addresses also specify locations for loading the program counter register\P, for transferring control, and for calling subroutines.

There are two main processes for calculating addresses


4. This machine is similar to the DEC PDP-11, but substantially simpler pedagogically. The PDP-11 manuals include ISP descriptions.


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