Transfer of Data from the RTM System to the Computer

Figure Cl-2c shows the flowchart of the RTM system for transmission to the minicomputer. The process is:

• 1. The RTM system first checks to see that the Outbuff is empty by waiting until the Outbuff-full flag is 0.

  2. The RTM system places a word in Outbuff and sets the Outbuff-full flag to 1.

  3. The Outbuff-full flag causes an interrupt to the minicomputer.

  4. The minicomputer reads the Outbuff indirectly via its C-input register and resets the Outbuff-full flag to 0, denoting that another word can be transmitted from the RTM system.

Note that a flowchart for the input and output processes in the minicomputer would be the opposite of those in the RTM system.

RTM-MINICOMPUTER INTERFACE VIA DIRECT MEMORY ACCESS TO COMPUTER

The structure of an interface which can be used by an RTM system to access directly the minicomputer's memory is given in Figure Cl-3a. The interface provides a capability that is essentially identical to that of the RTM system, i.e., having a large random access memory directly connected to its Bus. For this interface, standard minicomputer interface modules are not available directly; thus we simply postulate the registers and main functions. The control part of this interface is quite simple. The behavior of the interface is almost identical to the program controlled transfers except that hardware (within the minicomputer processor) controls the transfers instead of a program interpreted by the processor. Also, unlike the program controlled case, this channel is half-duplex; it can either transfer data to or from the computer's memory, but the transfers cannot be carried out simultaneously. This interface design is somewhat different from random access memories, even though. the computer provides an identical function, because a flag signifies when the transfer is complete (DC- request). By examining the DC-request condition the RTM system can carry out several steps while waiting for service since the computer may take several microseconds to respond with the data. The two macro processes for reading and writing are given in Figure Cl-3b and c. With the exception of the Kwait's, the behavior is identical to a random access memory.

Ps, A SPECIAL PROCESSOR TO SAMPLE ANALOG INPUT DATA AND COMPARE AGAINST LIMITS

Figure Ps-1 shows the structure and behavior of a special processor interfaced to a computer, which accepts analog data and checks the data against variable limits. The processor operates completely in parallel with a program in the computer, and the only interference is when the process accesses the computer's memory using the T(direct memory access). The structure of this hardwired process is similar to that of the hardwired processors in an IBM 1800. The process samples analog data, compares the data against high and low limits in a table, and signals when the out of limit condition occurs for each data point. The structure assumes that data is input-via an analog-to-digital converter with multiple selectable input channels. The data part also shows the various registers which the processor uses. The processor operates in much the same way as the processor of a stored program computer. There is a location in memory, k1, which contains an address of a data table That is interpreted as a

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