9. Modify Crtm-1 to include a Direct Memory Access (DMA) facility. With DMA, another system can communicate with a computer by reading directly into the computer's memory. Thus, the DMA provides a computer with the capability of behaving as an M(array).
10. Read about the two ERTM's described in the last section which assume program interrupt and DMA capabilities for a computer. Modify the two ERTM's to be compatible with the design of problems 8 and 9 above.
In this section we show how the DEC PDP-8, a common small minicomputer, can be implemented using RTM's. The goal of designing the PDP-8 from RTM's is mainly pedagogical. One would not expect to see a production, model computer constructed from RTM's due to considerations of production economy and technology.
The computer will be defined using ISP. In the implementation of any computer, we feel it is necessary to have a relatively formal (non-natural language text) description. Such a description enables the machine to be well defined. ISP satisfies this goal. Figure 8-1 gives the ISP description of the PDP 8, taken from Bell and Newell (1971).
A premise of, the RTM implementation is that one can take the formal description of the machine, in ISP (or some other language), and in an algorithmic fashion generate the implementation. In reality, we have not yet accomplished this goal, but the description will proceed in a quasi-formal way as though this were possible, and thus we will proceed to generate all the given parts from the ISP description. We are ignoring the various input-output devices.
For each register declared in the/ defining ISP description, a corresponding physical register is required to contain the actual condition. Using this procedure we get an RTM structure for the data part as shown in Figure 8-2. In this figure the two registers, AC\Accumulator and PC\Program Counter, of the ISP processor state are assigned to two DMgpa's. (In Crtm-i these were named A and P.) Two DMgpa's are used, not because of the innate character of AC or PC, but 'because of the operations to be performed upon them. We know that binary arithmetic and logical operations are performed on AC, necessitating a second operand register. Lack of the second operand register X<0:11>(2) would require undue movement of data to get the operands into the register to be operated on. Thus, we have made the first implicit design decision (which we hope will result in a short, simple control part). As the second decision, the PC is assigned to a second DMgpa, based on the knowledge that PC is to be incremented by one (i.e., it is a counter). For the time being, no other assignments are made to the second registers in the two DMgpa's, and they are considered to be temporary registers, X and z, being synonymous with the B registers of DMgpa's. We might expect that having an additional, separate DMgpa for the effective address calculation process (i.e. for z) would simplify the control; unfortunately it doesn't. There would only be one less Kevoke in the control part; therefore, we would rather increase the control part by one unit, in order to save an extra DMgpa.
2. Note, bits in the PDP-8 are numbered from left to right (most to least significant).