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needed in the interpretation of the instructions are: i, an instruction holding register; and B, a temporary register used for binary operations on A (e.g., ADD, AND). Also connected to the RTM Bus are the read-only and read-write memories and the Teletype, as well as a special input/output register interface to the remainder of the system. Instructions for manipulating these are left as an exercise for the student.

The method of defining the interpreter can be seen from the RTM diagram (Figure Crtm-5). The control part consists of four sub-parts: the start and continue keys, which are used to initialize the processor to start at location 0 and to restart the processor; the instruction fetch; the instruction decoder; and the instruction execution. The instruction fetch consists of picking up the instruction from the memory word addressed by the program Counter, P, and incrementing P to point to the next instruction. The instruction is placed in the register, which has been specially wired to a Kb8 to allow decoding of the three most significant bits. Individual bits of i can be tested for the Operate (OPR) instruction, and the address field, i<9:0>, can be read.

After the instruction is fetched and placed in i, Ke(MA<-i<9:0>) is evoked to address data referenced by the instruction. Immediately following this evoke operation, K(branch; 8-way) allows control to move to the one path corresponding to the operation code of the instruction being interpreted -- that is, the instruction is decoded and control is transferred to execute it. After the execution of the appropriate instruction, control returns to fetch the next instruction. For example, executing the ADD (two's complement add) instruction consists of loading the data from memory into the temporary register, B (i.e., B<-MB) and then adding B to the accumulator, A (i.e., A<-A+B).

For the Operate instruction, which does not reference memory, each bit of the address part of tie instruction specifies an operation to be carried out on the accumulator (test for - or 0, clear, complement, add one, shift right or left, or return from the subroutine). Each bit is tested in the sequence shown, and if a one, the corresponding operation is carried out. If the instruction code with op = 6 is given, the computer halts; pressing continue restarts it.

The instruction set shown above is straightforward and simple. Subroutine return addresses are stored in a link register, L. ,Thus to call subroutines at a depth of more than one level requires the called subroutine to save the link register in a. temporary location. But there is no way of storing this register; thus it is difficult to call a subroutine and pass parameter information (e.g., the location of data). A problem is given to correct these design faults.


The ISP notation can be used alone, in a linear text fashion, as an alternative description of the stored program computer. In fact, ISP was initially developed solely for the purpose of defining the instruction-set of a computer. The difference between an ISP and an RTM description appears fairly slight, with only a few more RTM actions required to implement the ISP. Also, an ISP description usually does not imply an implementation or structure. The main difference between the ISP and RTM description occurs because ISP is fundamentally a 1- dimensional or linear-text representation. For some descriptive applications this shortens the description, while in other cases the two are nearly the same size. The reader should not have a serious problem in understanding the ISP description because the various RTM register declarations and actions used in this book have been borrowed from ISP. The ISP description of Crtm-1 is given in Figure Crtm-6. In this description a Run-switch has been added for manually interrupting the computer.


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