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3.(2) Examine the feasibility of a digitally controlled, sampling switchboard for communications lines carrying {asynchronous| synchronous) communications data in the form found at the digital interface side of a modem (see Figure TRAN-8). Switching can be performed by sampling the incoming lines at a very high rate and transferring the samples to outgoing lines. The virtual interconnection of the links i and j is shown in Figure TRAN-9. Here, the receiver of i is connected to the transmitter of j and the receiver of j to the transmitter of i. The system would require a 1-bit memory for each half of each line at the transmitter, since the outgoing line must be held between sample times and the switching process consists of taking incoming samples at the receiver and passing them on to the transmitter bit.

The most important parameter of the design is to make the sampling process time, ts, for all the lines short so that a high sampling frequency is possible. The number of lines, n, that can be switched is a function of the maximum allowable distortion, d. The percentage of the variation in the bit-time the sampled transition times occurs and the bit data rate, r, determine d.

Another problem of the design is determining the control part of the system. As indicated in Figure TRAN-8, a standard full duplex communications link would give the control information concerning the switching paths. That is, the control link gives information designating that a line, i is to be connected to another line, j. This link could also transfer switch status information. The sampling switch uses this information to carry out the switching (by sampling). (Why each pair is to be connected is another story and problem.) The switching request information is usually contained on the incoming line. Thus information as to which incoming line is to be switched to another line is a difficult problem. You can determine designs which perhaps, ignore the problem-but hopefully you can solve it. Some solutions may require a modem signal that tells when a line is turned on.


Assuming that only a T(digital-to-analog) converter and a D(analog comparator) are available, design a family of T(analog-to-digital) converters. A D(analog comparator) has two analog inputs, I1 and I2, and one Boolean digital output. The relationship between output and input is B := I2 > I1; that is, if I2 < I1 then B will be false\0, and if I2 > I1, then B will be true \1.

By interconnecting these two components, finding a digital value corresponding to an analog input can be considered as a kind of guessing game. A digital value is given to the T(d-a), and the control for the conversion is able to find out whether the analog input is greater than or equal to the number given. Thus by systematic searching the value of the input can be found.

Examine various search strategies, determining the cost and conversion time. (Two obvious candidates are: t ~ k1 x input-value and t ~ k2 x logv2(b), where b is the number of bits in the answer.)



KEYWORDS: Synchronous, communications link, transmit, receive, modem, sample


2. This design was suggested by Mr. William Broadley, manager of the Carnegie Mellon University Computer Science Department Engineering Laboratory.


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